reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARC/ARCGenDAGISel.inc
 1192     return isUInt<6>(N->getSExtValue());
gen/lib/Target/AVR/AVRGenDAGISel.inc
 1674  return isUInt<6>(N->getZExtValue()); 
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc
72772   return isUInt<3>(v);
72781   return isUInt<3>(v);
72795   return Imm > 0 && isUInt<7>(Imm);
72860   return V % 8 == 0 && isUInt<3>(V / 8);
gen/lib/Target/Mips/MipsGenDAGISel.inc
30223 return isUInt<10>(Imm);
30229  return isUInt<7>(N->getZExtValue()); 
30236 return isUInt<4>(Imm);
30243 return isUInt<3>(Imm);
30250 return isUInt<2>(Imm);
30273 return isUInt<1>(Imm);
30333   return isUInt<5>(N->getZExtValue() - 1);
30341   return isUInt<5>(N->getZExtValue() - 33);
30349   return isUInt<5>(N->getZExtValue() - 32);
30368 return isUInt<2>(Imm - 1);
gen/lib/Target/Mips/MipsGenFastISel.inc
   21 return isUInt<4>(Imm);
   24 return isUInt<3>(Imm);
   27 return isUInt<2>(Imm);
   30 return isUInt<1>(Imm);
   33 return isUInt<4>(Imm);
gen/lib/Target/Mips/MipsGenGlobalISel.inc
  437     return isUInt<1>(Imm);
  442     return isUInt<10>(Imm);
  447     return isUInt<1>(Imm);
  452     return isUInt<2>(Imm);
  457     return isUInt<2>(Imm - 1);
  462     return isUInt<2>(Imm);
  472     return isUInt<3>(Imm);
  477     return isUInt<3>(Imm);
  482     return isUInt<4>(Imm);
  487     return isUInt<4>(Imm);
  539     return isUInt<1>(Imm);
  544     return isUInt<10>(Imm);
  549     return isUInt<1>(Imm);
  554     return isUInt<2>(Imm);
  559     return isUInt<2>(Imm);
  564     return isUInt<3>(Imm);
  569     return isUInt<3>(Imm);
  574     return isUInt<4>(Imm);
  579     return isUInt<4>(Imm);
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc
  105       return (Imm != 0) && (isUInt<5>(Imm) ||
  116       return  isUInt<6>(Imm) && (Imm != 0);
  117     return isUInt<5>(Imm) && (Imm != 0);
  939       return isUInt<20>(Imm);
  949       return  isUInt<6>(Imm);
  950     return isUInt<5>(Imm);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc
13963 return isUInt<5>(Imm);
13979     return isUInt<6>(Imm);
13980   return isUInt<5>(Imm);
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc
  137                                  (isUInt<5>(Imm) ||
  202     return isUInt<5>(Imm);
  229     return isUInt<6>(Imm);
  230   return isUInt<5>(Imm);
  238     return isUInt<6>(Imm) && (Imm != 0);
  239   return isUInt<5>(Imm) && (Imm != 0);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc
29861   return isUInt<4>(N->getZExtValue());
30014   return isUInt<3>(N->getZExtValue());
30022   return isUInt<2>(N->getZExtValue());
30030   return isUInt<1>(N->getZExtValue());
30421   return isUInt<12>(N->getZExtValue());
include/llvm/ADT/PointerEmbeddedInt.h
   64     assert((std::is_signed<IntT>::value ? isInt<Bits>(I) : isUInt<Bits>(I)) &&
include/llvm/Support/MathExtras.h
  398   return isUInt<N + S>(x) && (x % (UINT64_C(1) << S) == 0);
lib/CodeGen/MIRParser/MIParser.cpp
 1516   return isUInt<24>(AddrSpace);
lib/CodeGen/MachineVerifier.cpp
  864   if (!isUInt<6>(MI->getOperand(1).getImm()))
lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
  263       assert(isUInt<12>(Addend) && "Addend cannot be encoded.");
lib/IR/DataLayout.cpp
  226   if (!isUInt<24>(AddrSpace))
  275       if (!isUInt<24>(AddrSpace))
  492   if (!isUInt<24>(bit_width))
lib/MC/MCCodeView.cpp
  388   if (isUInt<7>(Data)) {
  393   if (isUInt<14>(Data)) {
  399   if (isUInt<29>(Data)) {
lib/Target/AArch64/AArch64ConditionalCompares.cpp
  330       if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
lib/Target/AArch64/AArch64FastISel.cpp
 1038            !isUInt<12>(Offset / ScaleFactor))
 1361   if (isUInt<12>(Imm))
lib/Target/AArch64/AArch64ISelLowering.cpp
 6128       if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
 6133       if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
 3718       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3724       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3730       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3736       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3742       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3748       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3754       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3764       PARSE_BITS_ENTRY(KD.kernel_code_properties,
 3768       PARSE_BITS_ENTRY(
 3773       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3777       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3781       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3785       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3789       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3799       if (!isUInt<1>(Val))
 3806       if (!isUInt<1>(Val))
 3813       if (!isUInt<1>(Val))
 3817       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
 3820       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
 3823       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
 3826       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
 3830       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
 3833       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE,
 3839       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,
 3845       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,
 3851       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,
 3857       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,
 3860       PARSE_BITS_ENTRY(
 3865       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3869       PARSE_BITS_ENTRY(
 3874       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3878       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3882       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3886       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
 3911   if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH>(
 3917   if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH>(
 3924   if (!isUInt<COMPUTE_PGM_RSRC2_USER_SGPR_COUNT_WIDTH>(UserSGPRCount))
 5723     if (Imm < 0 || !isUInt<4>(Imm)) {
 5970   return isImm() && isUInt<20>(getImm());
 6395   bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());
 6421   return isImm() && getImmTy() == ImmTyBLGP && isUInt<3>(getImm());
 6425   return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());
 6429   return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());
lib/Target/AMDGPU/SIFrameLowering.cpp
  105   if (isUInt<12>(Offset)) {
  152   if (isUInt<12>(Offset)) {
lib/Target/AMDGPU/SIISelLowering.cpp
 1080     return isUInt<11>(AM.BaseOffs) && AM.Scale == 0;
 1083   return isUInt<12>(AM.BaseOffs) && AM.Scale == 0;
 1116   if (!isUInt<12>(AM.BaseOffs))
 1178       if (!isUInt<20>(AM.BaseOffs))
lib/Target/AMDGPU/SIInstrInfo.cpp
 6294            (!Signed && isUInt<11>(Offset));
 6298          (!Signed && isUInt<12>(Offset));
lib/Target/AMDGPU/SIInstrInfo.h
 1004     return isUInt<12>(Imm);
lib/Target/AMDGPU/SIRegisterInfo.cpp
  339   return !isUInt<12>(FullOffset);
  407   assert(isUInt<12>(NewOffset) && "offset should be legal");
  421   return isUInt<12>(NewOffset);
  652   if (!isUInt<12>(Offset + Size - EltSize)) {
 1216         if (isUInt<12>(NewOffset) &&
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  731   return 0 <= Id && isUInt<ID_WIDTH_>(Id);
  735   return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);
  739   return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
  785     return 0 <= MsgId && isUInt<ID_WIDTH_>(MsgId);
  808     return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
  831     return 0 <= StreamId && isUInt<STREAM_ID_WIDTH_>(StreamId);
 1255     isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
lib/Target/ARC/ARCExpandPseudos.cpp
   64       isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
lib/Target/ARC/ARCFrameLowering.cpp
   65   if (isUInt<6>(AbsAmount))
  139     if (isUInt<6>(VarArgsBytes))
  188             TII->get(isUInt<6>(MFI.getStackSize()) ? ARC::ADD_rru6
  256     if (isUInt<6>(StackSize))
  284     if (isUInt<6>(MoveAmount))
  299     if (isUInt<6>(4 * StackSlotsUsedByFunclet))
  326     if (isUInt<6>(VarArgsBytes))
  457   if (isUInt<6>(NumBytes))
lib/Target/ARC/ARCOptAddrMode.cpp
  120 static bool isValidIncrementOffset(int64_t Off) { return isUInt<6>(Off); }
lib/Target/ARC/ARCRegisterInfo.cpp
   74     unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
  115             TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
lib/Target/ARM/ARMISelLowering.cpp
14884   return isUInt<5>(V / Scale);
14915       return isUInt<7>(V);
14932     return isUInt<12>(V);
14963     return isUInt<12>(V);
lib/Target/AVR/AVRFrameLowering.cpp
  129   unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK;
  200   if (isUInt<6>(FrameSize)) {
  393       if (isUInt<6>(Amount)) {
lib/Target/AVR/AVRISelDAGToDAG.cpp
  110     if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16)) {
lib/Target/AVR/AVRISelLowering.cpp
  762   if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) {
 1781       if (isUInt<6>(C->getZExtValue())) {
 1938       if (!isUInt<6>(CUVal64))
lib/Target/AVR/AVRRegisterInfo.cpp
  182       if (isUInt<6>(Offset)) {
  244   assert(isUInt<6>(Offset) && "Offset is out of range");
lib/Target/Hexagon/HexagonFrameLowering.cpp
 2527     return !isUInt<6>(StackSize >> MinLS);
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
 1099     if (isUInt<3>(MinSrc) || isUInt<3>(HwLen-MinSrc)) {
 1099     if (isUInt<3>(MinSrc) || isUInt<3>(HwLen-MinSrc)) {
 1100       bool IsRight = isUInt<3>(MinSrc); // Right align.
 2088     } else if (isUInt<3>(S)) {
lib/Target/Hexagon/HexagonInstrInfo.cpp
 2706     return isUInt<10>(Offset);
 2711     return isUInt<6>(Offset);
 2798     return isUInt<6>(Offset);
 3324         ((isUInt<5>(MI.getOperand(2).getImm())) ||
 3399   if (!isUInt<5>(V))
 3759         MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
 3788         isUInt<3>(MI.getOperand(2).getImm()))
 3872         MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
 3908         MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
 3915         MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
 3916         MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
 4020         MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
 4028         ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
 4030         isUInt<2>(MI.getOperand(1).getOffset()))) &&
 4031         ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
 4033         isUInt<2>(MI.getOperand(2).getOffset()))))
lib/Target/Hexagon/HexagonNewValueJump.cpp
  262         Valid = (isUInt<5>(v) || v == -1);
  266         Valid = isUInt<5>(v);
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
  196   return isUInt<N>(minConstant(MCI, Index));
lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
  340       return isUInt<21>(Value);
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
 1259     return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset);
 1272                               isUInt<Bits>(getConstantImm()))
 1334     return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
 1339     return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
lib/Target/Mips/Mips16InstrInfo.cpp
  229   if (isUInt<11>(FrameSize))
  256   if (!isUInt<11>(FrameSize)) {
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
  310   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
  311   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
  312   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
  313   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
  314   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
  316   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
  318                                   isUInt<6>(getImm()) &&
  320   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
  322                                   isUInt<7>(getImm()) &&
  329   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
  330   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
  391   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
  393     return Kind == Immediate && isUInt<6>(getImm());
  396                                        && isUInt<3>(getExprCRVal())) ||
  398                                        && isUInt<3>(getImm())); }
  400                                        && isUInt<5>(getExprCRVal())) ||
  402                                        && isUInt<5>(getImm())); }
lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  182   assert(isUInt<N>(Imm) && "Invalid immediate");
  190   assert(isUInt<N>(Imm) && "Invalid immediate");
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
 6090     if (!isUInt<15>(Op32.getConstantOperandVal(0)))
 6151     if (!isUInt<15>(Op32.getConstantOperandVal(1)))
 6189     bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
lib/Target/PowerPC/PPCInstrInfo.cpp
 2896     if (isUInt<15>(InVal.getSExtValue()) ||
 2921     bool ValueFits = isUInt<15>(InVal.getSExtValue());
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  389     return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
  389     return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
  402     return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
  402     return (isRV64() && isUInt<6>(Imm)) || isUInt<5>(Imm);
  411     return IsConstantImm && isUInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
  420     return IsConstantImm && isUInt<5>(Imm) && (Imm != 0) &&
  451            (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) &&
  550       return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None ||
  570       return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None ||
 1049       if (isUInt<12>(Imm)) {
lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  173   assert(isUInt<N>(Imm) && "Invalid immediate");
  191   assert(isUInt<N>(Imm) && "Invalid immediate");
  211   assert(isUInt<N>(Imm) && "Invalid immediate");
  222   assert(isUInt<6>(Imm) && "Invalid immediate");
  233   assert(isUInt<3>(Imm) && "Invalid immediate");
lib/Target/RISCV/RISCVISelLowering.cpp
 2709         if (isUInt<5>(CVal))
lib/Target/RISCV/RISCVInstrInfo.cpp
  508           Ok = isUInt<4>(Imm);
  511           Ok = isUInt<5>(Imm);
  514           Ok = isUInt<12>(Imm);
  523           Ok = isUInt<20>(Imm);
  530             Ok = isUInt<6>(Imm);
  532             Ok = isUInt<5>(Imm);
lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
  173   if (!isUInt<N>(Imm))
  252   assert(isUInt<N>(Imm) && "Invalid PC-relative offset");
lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
   68   assert(isUInt<N>(Value) && "Invalid uimm argument");
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp
  188   assert(isUInt<4>(Base) && isUInt<12>(Disp));
  188   assert(isUInt<4>(Base) && isUInt<12>(Disp));
  198   assert(isUInt<4>(Base) && isInt<20>(Disp));
  209   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
  209   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
  209   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
  220   assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
  220   assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
  232   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
  232   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
  232   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
  243   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
  243   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
  254   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
  254   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
  254   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len));
  265   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
  265   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
  265   assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index));
lib/Target/SystemZ/SystemZFrameLowering.cpp
  302   if (!isUInt<12>(MaxReach)) {
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
  386     return isUInt<12>(Val);
  504     return isUInt<12>(Val);
  508     return !isUInt<12>(Val);
  532     if (isUInt<12>(Disp))
lib/Target/SystemZ/SystemZISelLowering.cpp
  920   if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs))
 1027       if (isUInt<12>(C->getZExtValue()))
 1167         if (isUInt<12>(C->getZExtValue()))
 7350     if (!isUInt<12>(DestDisp)) {
 7359     if (!isUInt<12>(SrcDisp)) {
lib/Target/SystemZ/SystemZInstrInfo.cpp
  905           isUInt<12>(MI->getOperand(2).getImm()) &&
 1505   if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
 1505   if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
lib/Target/X86/AsmParser/X86AsmParserCommon.h
   39   return isUInt<4>(Value);
tools/lld/ELF/Arch/ARM.cpp
  195   if (!llvm::isUInt<27>(offset)) {
  248   if (!llvm::isUInt<27>(offset)) {
tools/lld/ELF/InputFiles.cpp
  880     assert(isUInt<31>(target->numRelocations));