|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenDAGISel.inc35609 /* 78512*/ OPC_CheckValueType, MVT::v4i8,
gen/lib/Target/Hexagon/HexagonGenCallingConv.inc 71 LocVT == MVT::v4i8) {
115 LocVT == MVT::v4i8) {
279 LocVT == MVT::v4i8) {
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc17176 /* 32893*/ OPC_CheckChild1Type, MVT::v4i8,
24529 /* 47167*/ /*SwitchType*/ 8, MVT::v4i8,// ->47177
24531 MVT::v4i8, 2/*#Ops*/, 0, 1,
26021 /* 49960*/ /*SwitchType*/ 71, MVT::v4i8,// ->50033
26040 MVT::v4i8, 2/*#Ops*/, 12, 13,
26564 /* 51017*/ /*SwitchType*/ 71, MVT::v4i8,// ->51090
26583 MVT::v4i8, 2/*#Ops*/, 12, 13,
28829 /* 55644*/ /*SwitchType*/ 8, MVT::v4i8,// ->55654
28831 MVT::v4i8, 2/*#Ops*/, 0, 1,
52505 /* 99081*/ OPC_CheckChild0Type, MVT::v4i8,
52605 /* 99310*/ /*SwitchType*/ 32, MVT::v4i8,// ->99344
52613 MVT::v4i8, 2/*#Ops*/, 3, 4,
52695 /* 99513*/ OPC_CheckChild2Type, MVT::v4i8,
52918 /* 99921*/ OPC_CheckChild2Type, MVT::v4i8,
53234 /*100527*/ OPC_CheckChild2Type, MVT::v4i8,
53498 /*101030*/ OPC_CheckChild2Type, MVT::v4i8,
55123 /*104069*/ /*SwitchType*/ 8, MVT::v4i8,// ->104079
55125 MVT::v4i8, 2/*#Ops*/, 0, 1,
60009 /*114682*/ /*SwitchType*/ 11, MVT::v4i8,// ->114695
60013 MVT::v4i8, 1/*#Ops*/, 2,
60129 /*114917*/ /*SwitchType*/ 15, MVT::v4i8,// ->114934
60134 MVT::v4i8, 3/*#Ops*/, 1, 5, 4,
60251 /*115162*/ /*SwitchType*/ 15, MVT::v4i8,// ->115179
60256 MVT::v4i8, 3/*#Ops*/, 2, 5, 4,
60298 /*115255*/ /*SwitchType*/ 11, MVT::v4i8,// ->115268
60302 MVT::v4i8, 1/*#Ops*/, 2,
60531 /*115678*/ /*SwitchType*/ 12, MVT::v4i8,// ->115692
60535 MVT::v4i8, 3/*#Ops*/, 1, 2, 4,
60583 /*115775*/ /*SwitchType*/ 12, MVT::v4i8,// ->115789
60587 MVT::v4i8, 3/*#Ops*/, 3, 1, 4,
60691 /*115992*/ /*SwitchType*/ 15, MVT::v4i8,// ->116009
60696 MVT::v4i8, 2/*#Ops*/, 3, 4,
60797 /*116211*/ /*SwitchType*/ 15, MVT::v4i8,// ->116228
60802 MVT::v4i8, 2/*#Ops*/, 4, 3,
60896 /*116409*/ /*SwitchType*/ 12, MVT::v4i8,// ->116423
60900 MVT::v4i8, 2/*#Ops*/, 1, 3,
60991 /*116595*/ /*SwitchType*/ 12, MVT::v4i8,// ->116609
60995 MVT::v4i8, 2/*#Ops*/, 2, 3,
61272 /*117146*/ /*SwitchType*/ 15, MVT::v4i8,// ->117163
61277 MVT::v4i8, 2/*#Ops*/, 3, 4,
61378 /*117365*/ /*SwitchType*/ 15, MVT::v4i8,// ->117382
61383 MVT::v4i8, 2/*#Ops*/, 4, 3,
61477 /*117563*/ /*SwitchType*/ 12, MVT::v4i8,// ->117577
61481 MVT::v4i8, 2/*#Ops*/, 1, 3,
61572 /*117749*/ /*SwitchType*/ 12, MVT::v4i8,// ->117763
61576 MVT::v4i8, 2/*#Ops*/, 2, 3,
61680 /*117966*/ /*SwitchType*/ 15, MVT::v4i8,// ->117983
61685 MVT::v4i8, 2/*#Ops*/, 2, 3,
61730 /*118066*/ /*SwitchType*/ 13, MVT::v4i8,// ->118081
61734 MVT::v4i8, 3/*#Ops*/, 1, 2, 3,
61829 /*118264*/ /*SwitchType*/ 12, MVT::v4i8,// ->118278
61833 MVT::v4i8, 2/*#Ops*/, 1, 2,
64013 /*122824*/ /*SwitchType*/ 7, MVT::v4i8,// ->122833
64015 MVT::v4i8, 1/*#Ops*/, 0,
64768 /*124479*/ OPC_CheckType, MVT::v4i8,
64772 MVT::v4i8, 1/*#Ops*/, 2,
66597 /*127980*/ /*SwitchType*/ 3, MVT::v4i8,// ->127985
66603 /*127987*/ OPC_CheckChild0Type, MVT::v4i8,
66668 /*128075*/ /*SwitchType*/ 3, MVT::v4i8,// ->128080
67218 /*129154*/ OPC_CheckChild0Type, MVT::v4i8,
67280 /*129267*/ /*SwitchType*/ 14, MVT::v4i8,// ->129283
67284 MVT::v4i8, 1/*#Ops*/, 1,
67319 /*129358*/ OPC_CheckChild0Type, MVT::v4i8,
67375 /*129509*/ /*SwitchType*/ 32, MVT::v4i8,// ->129543
67383 MVT::v4i8, 2/*#Ops*/, 3, 4,
70005 /*135638*/ OPC_CheckType, MVT::v4i8,
70007 MVT::v4i8, 1/*#Ops*/, 0,
72834 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::v4i8;
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2340 /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
2344 /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
gen/lib/Target/Mips/MipsGenDAGISel.inc 557 /* 917*/ OPC_CheckChild1Type, MVT::v4i8,
1338 /* 2388*/ /*SwitchType*/ 25, MVT::v4i8,// ->2415
1346 MVT::v4i8, 2/*#Ops*/, 4, 5,
7471 MVT::v4i8, 2/*#Ops*/, 1, 3,
7478 MVT::v4i8, 2/*#Ops*/, 1, 2,
7485 MVT::v4i8, 2/*#Ops*/, 1, 2,
7534 MVT::v4i8, 2/*#Ops*/, 1, 2,
7541 MVT::v4i8, 2/*#Ops*/, 1, 2,
7610 MVT::v4i8, 2/*#Ops*/, 1, 2,
7617 MVT::v4i8, 2/*#Ops*/, 1, 2,
7723 MVT::v4i8, 1/*#Ops*/, 1,
7730 MVT::v4i8, 1/*#Ops*/, 1,
7780 MVT::v4i8, 2/*#Ops*/, 1, 2,
7787 MVT::v4i8, 2/*#Ops*/, 1, 2,
8106 MVT::v4i8, 1/*#Ops*/, 1,
8113 MVT::v4i8, 1/*#Ops*/, 1,
8120 MVT::v4i8, 1/*#Ops*/, 0,
8126 MVT::v4i8, 1/*#Ops*/, 0,
8223 MVT::v4i8, 2/*#Ops*/, 0, 2,
8230 MVT::v4i8, 2/*#Ops*/, 0, 2,
8237 MVT::v4i8, 2/*#Ops*/, 0, 1,
8243 MVT::v4i8, 2/*#Ops*/, 0, 1,
8315 MVT::v4i8, 2/*#Ops*/, 0, 2,
8321 MVT::v4i8, 2/*#Ops*/, 0, 1,
8327 MVT::v4i8, 2/*#Ops*/, 0, 1,
8343 MVT::v4i8, 2/*#Ops*/, 0, 2,
8349 MVT::v4i8, 2/*#Ops*/, 0, 1,
8355 MVT::v4i8, 2/*#Ops*/, 0, 1,
8630 MVT::v4i8, 2/*#Ops*/, 0, 1,
8636 MVT::v4i8, 2/*#Ops*/, 0, 1,
8647 MVT::v4i8, 2/*#Ops*/, 0, 1,
8653 MVT::v4i8, 2/*#Ops*/, 0, 1,
8698 MVT::v4i8, 2/*#Ops*/, 0, 1,
8704 MVT::v4i8, 2/*#Ops*/, 0, 1,
8877 MVT::v4i8, 2/*#Ops*/, 0, 1,
8883 MVT::v4i8, 2/*#Ops*/, 0, 1,
8894 MVT::v4i8, 2/*#Ops*/, 0, 1,
8900 MVT::v4i8, 2/*#Ops*/, 0, 1,
8911 MVT::v4i8, 2/*#Ops*/, 0, 1,
8917 MVT::v4i8, 2/*#Ops*/, 0, 1,
8928 MVT::v4i8, 2/*#Ops*/, 0, 1,
8934 MVT::v4i8, 2/*#Ops*/, 0, 1,
9030 MVT::v4i8, 2/*#Ops*/, 0, 1,
9039 MVT::v4i8, 2/*#Ops*/, 0, 1,
16088 /* 29696*/ /*SwitchType*/ 10, MVT::v4i8,// ->29708
16091 MVT::v4i8, 2/*#Ops*/, 0, 1,
18325 /* 34314*/ /*SwitchType*/ 10, MVT::v4i8,// ->34326
18328 MVT::v4i8, 2/*#Ops*/, 0, 1,
24690 /* 46235*/ /*SwitchType*/ 13, MVT::v4i8,// ->46250
24694 MVT::v4i8, 2/*#Ops*/, 0, 1,
24724 /* 46301*/ OPC_CheckChild0Type, MVT::v4i8,
24769 /* 46388*/ /*SwitchType*/ 13, MVT::v4i8,// ->46403
24773 MVT::v4i8, 2/*#Ops*/, 0, 1,
28961 /* 54784*/ /*SwitchType*/ 12, MVT::v4i8,// ->54798
28965 MVT::v4i8, 2/*#Ops*/, 0, 2,
28982 /* 54824*/ /*SwitchType*/ 12, MVT::v4i8,// ->54838
28986 MVT::v4i8, 2/*#Ops*/, 0, 2,
29003 /* 54864*/ /*SwitchType*/ 12, MVT::v4i8,// ->54878
29007 MVT::v4i8, 2/*#Ops*/, 0, 2,
29382 /* 55598*/ OPC_CheckChild0Type, MVT::v4i8,
29390 /* 55609*/ OPC_CheckType, MVT::v4i8,
29393 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
29395 MVT::v4i8, 3/*#Ops*/, 4, 2, 3,
29401 /* 55634*/ OPC_CheckType, MVT::v4i8,
29404 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
29406 MVT::v4i8, 3/*#Ops*/, 4, 2, 3,
29412 /* 55659*/ OPC_CheckType, MVT::v4i8,
29415 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
29417 MVT::v4i8, 3/*#Ops*/, 4, 2, 3,
29423 /* 55684*/ OPC_CheckType, MVT::v4i8,
29426 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
29428 MVT::v4i8, 3/*#Ops*/, 4, 3, 2,
29434 /* 55709*/ OPC_CheckType, MVT::v4i8,
29437 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
29439 MVT::v4i8, 3/*#Ops*/, 4, 3, 2,
29445 /* 55734*/ OPC_CheckType, MVT::v4i8,
29448 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
29450 MVT::v4i8, 3/*#Ops*/, 4, 3, 2,
29563 /* 56125*/ /*SwitchType*/ 103|128,2/*359*/, MVT::v4i8,// ->56487
29564 /* 56128*/ OPC_CheckChild0Type, MVT::v4i8,
29570 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
29577 MVT::v4i8, 2/*#Ops*/, 5, 6, // Results = #7
29578 /* 56179*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29580 MVT::v4i8, 3/*#Ops*/, 2, 7, 8,
29587 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
29594 MVT::v4i8, 2/*#Ops*/, 5, 6, // Results = #7
29595 /* 56238*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29597 MVT::v4i8, 3/*#Ops*/, 2, 7, 8,
29604 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
29611 MVT::v4i8, 2/*#Ops*/, 5, 6, // Results = #7
29612 /* 56297*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29614 MVT::v4i8, 3/*#Ops*/, 2, 7, 8,
29621 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
29622 /* 56322*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29629 MVT::v4i8, 2/*#Ops*/, 6, 7, // Results = #8
29631 MVT::v4i8, 3/*#Ops*/, 2, 3, 8,
29638 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
29639 /* 56381*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29646 MVT::v4i8, 2/*#Ops*/, 6, 7, // Results = #8
29648 MVT::v4i8, 3/*#Ops*/, 2, 3, 8,
29655 MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
29656 /* 56440*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
29663 MVT::v4i8, 2/*#Ops*/, 6, 7, // Results = #8
29665 MVT::v4i8, 3/*#Ops*/, 2, 3, 8,
gen/lib/Target/Mips/MipsGenFastISel.inc 1255 if (RetVT.SimpleTy != MVT::v4i8)
1312 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
2401 if (RetVT.SimpleTy != MVT::v4i8)
2458 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
3477 if (RetVT.SimpleTy != MVT::v4i8)
3496 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3505 if (RetVT.SimpleTy != MVT::v4i8)
3524 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
3533 if (RetVT.SimpleTy != MVT::v4i8)
3552 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3928 /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 1851 /* 16 */ MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
include/llvm/Support/MachineValueType.h 335 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 ||
447 case v4i8:
617 case v4i8:
716 case v4i8:
918 if (NumElements == 4) return MVT::v4i8;
lib/CodeGen/ValueTypes.cpp 152 case MVT::v4i8: return "v4i8";
296 case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4);
lib/Target/AArch64/AArch64ISelLowering.cpp 698 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
699 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
801 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
2626 case MVT::v4i8:
2901 assert(MemVT == MVT::v4i8 && VT == MVT::v4i16);
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 335 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
337 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
377 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
379 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 138 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
139 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
lib/Target/AMDGPU/R600ISelLowering.cpp 112 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
190 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 189 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
219 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
313 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
669 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
lib/Target/ARM/ARMISelDAGToDAG.cpp 1653 } else if (LoadedVT == MVT::v4i8 &&
lib/Target/ARM/ARMISelLowering.cpp 367 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
371 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
379 setIndexedLoadAction(im, MVT::v4i8, Legal);
380 setIndexedStoreAction(im, MVT::v4i8, Legal);
911 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
8297 case MVT::v4i8:
14612 if ((Ty == MVT::v4i8 || Ty == MVT::v8i8 || Ty == MVT::v4i16) &&
15239 } else if (VT == MVT::v4i8 || VT == MVT::v8i8) {
lib/Target/ARM/ARMTargetTransformInfo.cpp 197 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0},
198 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0},
249 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
250 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
264 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
265 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
362 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
363 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 97 case MVT::v4i8:
487 case MVT::v4i8:
lib/Target/Hexagon/HexagonISelLowering.cpp 556 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
818 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
876 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1271 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1317 setOperationAction(ISD::SETCC, MVT::v4i8, Custom);
1472 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1473 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1474 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1477 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1498 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1504 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1518 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
1520 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1549 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
2161 return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2196 return DAG.getBitcast(MVT::v4i8, R);
lib/Target/Hexagon/HexagonInstrInfo.cpp 2653 case MVT::v4i8:
lib/Target/Mips/MipsSEISelLowering.cpp 85 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
874 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
931 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
943 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
970 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
983 if (Ty == MVT::v2i16 || Ty == MVT::v4i8) {
lib/Target/NVPTX/NVPTXISelLowering.cpp 140 case MVT::v4i8:
2309 case MVT::v4i8:
4510 if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4800 case MVT::v4i8:
lib/Target/PowerPC/PPCISelLowering.cpp 686 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
843 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
847 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
lib/Target/X86/X86ISelLowering.cpp 846 for (auto VT : { MVT::v2i8, MVT::v4i8, MVT::v8i8,
855 setOperationAction(ISD::MUL, MVT::v4i8, Custom);
939 setOperationAction(ISD::FP_TO_SINT, MVT::v4i8, Custom);
944 setOperationAction(ISD::FP_TO_UINT, MVT::v4i8, Custom);
993 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
1065 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i8, Legal);
1241 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i8, Legal);
1727 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1736 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
28012 if (InVT == MVT::v4i64 && VT == MVT::v4i8 && isTypeLegal(MVT::v8i64)) {
28050 (InVT == MVT::v4i16 || InVT == MVT::v4i8)){
36291 if (VecVT == MVT::v4i8 || VecVT == MVT::v8i8) {
36292 if (VecVT == MVT::v4i8) {
lib/Target/X86/X86TargetTransformInfo.cpp 1370 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1412 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 1 },
1413 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 },
1425 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 2 },
1443 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1444 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1459 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i64, 4 },
1470 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
1471 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
1483 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
1484 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
1503 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
1518 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1519 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1525 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1526 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 2 },
1527 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1528 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1544 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 2 },
1546 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 1 },
1585 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1586 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },
1587 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
1588 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 3 },
1589 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1590 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 8 },
1611 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i16, 4 },
1616 { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 3 },
2547 { ISD::ADD, MVT::v4i8, 2 },
2572 { ISD::ADD, MVT::v4i8, 2 },
3545 { 3, MVT::v4i8, 4 }, //(load 12i8 and) deinterleave into 3 x 4i8
3552 { 4, MVT::v4i8, 4 }, //(load 16i8 and) deinterleave into 4 x 4i8
3565 { 3, MVT::v4i8, 8 }, //interleave 3 x 4i8 into 12i8 (and store)
3571 { 4, MVT::v4i8, 9 }, //interleave 4 x 4i8 into 16i8 (and store)
utils/TableGen/CodeGenTarget.cpp 92 case MVT::v4i8: return "MVT::v4i8";