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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/X86/X86GenRegisterInfo.inc 15 class MCRegisterClass;
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 15 class MCRegisterClass;
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 35 class MCRegisterClass;
References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 16 extern const MCRegisterClass AArch64MCRegisterClasses[];
3436 extern const MCRegisterClass AArch64MCRegisterClasses[] = {
5177 extern const MCRegisterClass AArch64MCRegisterClasses[];
6812 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
6826 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
6840 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
6854 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
6868 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
6882 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc 16 extern const MCRegisterClass AMDGPUMCRegisterClasses[];
11242 extern const MCRegisterClass AMDGPUMCRegisterClasses[] = {
17456 extern const MCRegisterClass AMDGPUMCRegisterClasses[];
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 16 extern const MCRegisterClass R600MCRegisterClasses[];
7042 extern const MCRegisterClass R600MCRegisterClasses[] = {
8866 extern const MCRegisterClass R600MCRegisterClasses[];
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 16 extern const MCRegisterClass ARCMCRegisterClasses[];
262 extern const MCRegisterClass ARCMCRegisterClasses[] = {
552 extern const MCRegisterClass ARCMCRegisterClasses[];
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 16 extern const MCRegisterClass ARMMCRegisterClasses[];
2890 extern const MCRegisterClass ARMMCRegisterClasses[] = {
3743 extern const MCRegisterClass ARMMCRegisterClasses[];
5905 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID];
5923 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID];
5942 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID];
5961 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID];
5979 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRRegClassID];
5998 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID];
6017 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRnospRegClassID];
6036 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID];
6054 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREvenRegClassID];
6070 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPROddRegClassID];
6086 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID];
6102 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tGPREvenRegClassID];
6118 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tGPROddRegClassID];
6134 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tcGPRRegClassID];
6150 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREven_and_tcGPRRegClassID];
6165 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tGPROddRegClassID];
6181 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREven_and_tGPR_and_tcGPRRegClassID];
6197 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPROdd_and_tcGPRRegClassID];
6212 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tcGPRRegClassID];
6229 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPRRegClassID];
6247 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPairRegClassID];
6265 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_0RegClassID];
6283 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QPRRegClassID];
6301 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_2RegClassID];
6319 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_0_in_DPR_8RegClassID];
6337 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_1_in_DPR_8RegClassID];
6352 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQPRRegClassID];
6366 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_MQPRRegClassID];
6380 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_MQPRRegClassID];
6394 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_8RegClassID];
6408 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_8RegClassID];
6422 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPRRegClassID];
6436 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_0RegClassID];
6450 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_4RegClassID];
6464 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_8RegClassID];
6478 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_12RegClassID];
6492 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID];
6506 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID];
6520 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID];
6534 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID];
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 16 extern const MCRegisterClass AVRMCRegisterClasses[];
531 extern const MCRegisterClass AVRMCRegisterClasses[] = {
914 extern const MCRegisterClass AVRMCRegisterClasses[];
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 16 extern const MCRegisterClass BPFMCRegisterClasses[];
207 extern const MCRegisterClass BPFMCRegisterClasses[] = {
428 extern const MCRegisterClass BPFMCRegisterClasses[];
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 16 extern const MCRegisterClass HexagonMCRegisterClasses[];
1279 extern const MCRegisterClass HexagonMCRegisterClasses[] = {
2336 extern const MCRegisterClass HexagonMCRegisterClasses[];
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 16 extern const MCRegisterClass LanaiMCRegisterClasses[];
301 extern const MCRegisterClass LanaiMCRegisterClasses[] = {
610 extern const MCRegisterClass LanaiMCRegisterClasses[];
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 16 extern const MCRegisterClass MSP430MCRegisterClasses[];
241 extern const MCRegisterClass MSP430MCRegisterClasses[] = {
353 extern const MCRegisterClass MSP430MCRegisterClasses[];
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 16 extern const MCRegisterClass MipsMCRegisterClasses[];
2673 extern const MCRegisterClass MipsMCRegisterClasses[] = {
3919 extern const MCRegisterClass MipsMCRegisterClasses[];
4767 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
4784 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 16 extern const MCRegisterClass NVPTXMCRegisterClasses[];
614 extern const MCRegisterClass NVPTXMCRegisterClasses[] = {
807 extern const MCRegisterClass NVPTXMCRegisterClasses[];
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 16 extern const MCRegisterClass PPCMCRegisterClasses[];
1707 extern const MCRegisterClass PPCMCRegisterClasses[] = {
3917 extern const MCRegisterClass PPCMCRegisterClasses[];
4278 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
4294 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];
4310 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];
4326 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];
4342 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];
4358 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_and_G8RC_NOX0RegClassID];
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 16 extern const MCRegisterClass RISCVMCRegisterClasses[];
605 extern const MCRegisterClass RISCVMCRegisterClasses[] = {
1166 extern const MCRegisterClass RISCVMCRegisterClasses[];
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 16 extern const MCRegisterClass SparcMCRegisterClasses[];
1234 extern const MCRegisterClass SparcMCRegisterClasses[] = {
1940 extern const MCRegisterClass SparcMCRegisterClasses[];
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 16 extern const MCRegisterClass SystemZMCRegisterClasses[];
1100 extern const MCRegisterClass SystemZMCRegisterClasses[] = {
1843 extern const MCRegisterClass SystemZMCRegisterClasses[];
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 16 extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
203 extern const MCRegisterClass WebAssemblyMCRegisterClasses[] = {
299 extern const MCRegisterClass WebAssemblyMCRegisterClasses[];
gen/lib/Target/X86/X86GenRegisterInfo.inc 16 extern const MCRegisterClass X86MCRegisterClasses[];
2589 extern const MCRegisterClass X86MCRegisterClasses[] = {
4469 extern const MCRegisterClass X86MCRegisterClasses[];
6256 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
6272 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 16 extern const MCRegisterClass XCoreMCRegisterClasses[];
170 extern const MCRegisterClass XCoreMCRegisterClasses[] = {
371 extern const MCRegisterClass XCoreMCRegisterClasses[];
include/llvm/CodeGen/TargetRegisterInfo.h 51 const MCRegisterClass *MC;
include/llvm/MC/MCRegisterInfo.h 128 using regclass_iterator = const MCRegisterClass *;
151 const MCRegisterClass *Classes; // Pointer to the regclass array
238 const MCRegisterClass *C, unsigned NC,
349 const MCRegisterClass *RC) const;
426 const MCRegisterClass& getRegClass(unsigned i) const {
431 const char *getRegClassName(const MCRegisterClass *Class) const {
lib/MC/MCRegisterInfo.cpp 25 const MCRegisterClass *RC) const {
lib/MCA/HardwareUnits/RegisterFile.cpp 88 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID);
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 3928 auto PPRRegClass = AArch64MCRegisterClasses[AArch64::PPRRegClassID];
5603 const MCRegisterClass &WRegClass =
5605 const MCRegisterClass &XRegClass =
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 1285 const MCRegisterClass &FPR128RC =
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 2134 const MCRegisterClass RC = TRI->getRegClass(RCID);
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 626 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 958 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
1128 unsigned getRegBitWidth(const MCRegisterClass &RC) {
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 572 unsigned getRegBitWidth(const MCRegisterClass &RC);
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 3173 const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID];
3174 const MCRegisterClass *RC_out = (VectorList.Count == 2) ?
4308 const MCRegisterClass *RC;
4729 const MCRegisterClass *RC = (Spacing == 1) ?
6725 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
7102 const MCRegisterClass &MRC = MRI->getRegClass(ARM::GPRRegClassID);
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 261 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID);
lib/Target/AVR/AsmParser/AVRAsmParser.cpp 77 MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
lib/Target/BPF/BPFMIChecking.cpp 107 const MCRegisterClass *GPR64RegClass =
lib/Target/Mips/MipsOptionRecord.h 66 const MCRegisterClass *GPR32RegClass;
67 const MCRegisterClass *GPR64RegClass;
68 const MCRegisterClass *FGR32RegClass;
69 const MCRegisterClass *FGR64RegClass;
70 const MCRegisterClass *AFGR64RegClass;
71 const MCRegisterClass *MSA128BRegClass;
72 const MCRegisterClass *COP0RegClass;
73 const MCRegisterClass *COP2RegClass;
74 const MCRegisterClass *COP3RegClass;
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 428 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
429 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
430 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
tools/llvm-exegesis/lib/RegisterAliasing.cpp 33 const MCRegisterClass &RegClass)
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex);
tools/llvm-exegesis/lib/RegisterAliasing.h 45 const MCRegisterClass &RegClass);
usr/include/c++/7.4.0/bits/range_access.h 58 begin(const _Container& __cont) -> decltype(__cont.begin())
78 end(const _Container& __cont) -> decltype(__cont.end())