reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/GlobalISel/Utils.cpp

   92     assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&

lib/CodeGen/MachineVerifier.cpp

 1528   if (isPreISelGenericOpcode(MCID.getOpcode())) {
 1597   if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
 1760         if (!isPreISelGenericOpcode(MCID.getOpcode()) &&

lib/Target/AArch64/AArch64InstrInfo.cpp

   94   switch (Desc.getOpcode()) {

lib/Target/AArch64/AArch64SIMDInstrOpt.cpp

  223   auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget);
  253     ReplCost += SchedModel.computeInstrLatency(IDesc->getOpcode());
  255   if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost)
  444     if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) {
  456     if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg1, LaneNumber, &DupDest)) {

lib/Target/AMDGPU/SIInstrInfo.cpp

 1728   unsigned Opc = Desc.getOpcode();
 3427   if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
 3489   if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
 3514   if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
 3515       Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
 3569   if (Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e32 ||
 3570       Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e64 ||
 3571       Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
 3572       Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64) {
 3573     const bool IsDst = Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
 3574                        Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64;

lib/Target/ARM/ARMBaseInstrInfo.cpp

 3767     switch (DefMCID.getOpcode()) {
 3858     switch (UseMCID.getOpcode()) {
 3925   switch (DefMCID.getOpcode()) {
 3966   switch (UseMCID.getOpcode()) {
 4082     switch (DefMCID.getOpcode()) {
 4107     switch (DefMCID.getOpcode()) {
 4138     switch (DefMCID.getOpcode()) {
 4386     switch (DefMCID.getOpcode()) {
 4413     switch (DefMCID.getOpcode()) {
 4439     switch (DefMCID.getOpcode()) {

lib/Target/ARM/ARMHazardRecognizer.cpp

   25   unsigned Opcode = MCID.getOpcode();

lib/Target/ARM/ARMISelDAGToDAG.cpp

  452     unsigned Opcode = MCID.getOpcode();

lib/Target/ARM/MLxExpansionPass.cpp

  188   unsigned Opcode = MCID.getOpcode();
  356       if (!TII->isFpMLxInstruction(MCID.getOpcode(),

lib/Target/ARM/Thumb2SizeReduction.cpp

  920   if (MCID.getOpcode() == ARM::t2TEQrr) {
  940     if ((MCID.getOpcode() == ARM::t2RSBSri ||
  941          MCID.getOpcode() == ARM::t2RSBri ||
  942          MCID.getOpcode() == ARM::t2SXTB ||
  943          MCID.getOpcode() == ARM::t2SXTH ||
  944          MCID.getOpcode() == ARM::t2UXTB ||
  945          MCID.getOpcode() == ARM::t2UXTH) && i == 2)

lib/Target/AVR/AVRInstrInfo.cpp

  352         unsigned JNCC = getBrCond(BranchCode).getOpcode();

lib/Target/Hexagon/HexagonInstrInfo.cpp

 2016          MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
 2017          MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&

lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp

  538   switch (MCID.getOpcode()) {
  628   unsigned Opc = MCID.getOpcode();

lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp

  662              << HexagonMCInstrInfo::getDesc(MCII, ISJ->getDesc()).getOpcode();

lib/Target/MSP430/MSP430InstrInfo.cpp

  303   switch (Desc.getOpcode()) {

lib/Target/Mips/Mips16InstrInfo.cpp

  148   switch (MI.getDesc().getOpcode()) {

lib/Target/Mips/MipsConstantIslandPass.cpp

 1646       switch(I->getDesc().getOpcode()) {

lib/Target/Mips/MipsSEInstrInfo.cpp

  413   switch (MI.getDesc().getOpcode()) {

lib/Target/PowerPC/PPCHazardRecognizers.cpp

  123   if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

  340     if (Desc.getOpcode() == RISCV::JAL) {

tools/llvm-exegesis/lib/CodeTemplate.cpp

   32   return Instr.Description->getOpcode();

tools/llvm-exegesis/lib/Latency.cpp

   52     if (OtherOpcode == Instr.Description->getOpcode())

tools/llvm-exegesis/lib/X86/Target.cpp

  262   const auto Opcode = Instr.Description->getOpcode();
  313   const auto Opcode = Instr.Description->getOpcode();