reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc

 9132   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

25782   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc

11494   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 8552   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/AVR/AVRGenRegisterInfo.inc

 1472   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/BPF/BPFGenRegisterInfo.inc

  563   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 3230   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc

  783   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc

  496   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 6211   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc

 5209   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc

 1637   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Sparc/SparcGenRegisterInfo.inc

 2536   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc

 2623   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/X86/X86GenRegisterInfo.inc

 8158   LaneMask &= getSubRegIndexLaneMask(IdxA);

include/llvm/CodeGen/RegisterPressure.h

  324     I->LaneMask &= ~Pair.LaneMask;

lib/CodeGen/DetectDeadLanes.cpp

  204   UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg);
  318     DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
  325       DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
  329       DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
  348   DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());

lib/CodeGen/LiveInterval.cpp

  951     ToApply &= ~Matching;

lib/CodeGen/MachineBasicBlock.cpp

  454   I->LaneMask &= ~LaneMask;

lib/CodeGen/RegisterCoalescer.cpp

 1392         MaxMask &= ~SR.LaneMask;
 2617       OtherV.ValidLanes &= ~OtherV.WriteLanes;
 2641     V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
 2816     TaintedLanes &= ~OV.WriteLanes;

lib/CodeGen/RegisterPressure.cpp

  415     I->LaneMask &= ~Pair.LaneMask;
 1235       LastUseMask &= ~UseMask;

lib/CodeGen/ScheduleDAGInstrs.cpp

  410           KillLaneMask &= ~getLaneMaskForMO(OtherMO);
  446       LaneMask &= ~KillLaneMask;

lib/CodeGen/SplitKit.cpp

  621     LanesLeft &= ~TRI.getSubRegIndexLaneMask(BestIdx);

lib/Target/AMDGPU/GCNRegPressure.cpp

  340     LiveMask &= ~getDefRegMask(MO, *MRI);
  384           It.second &= ~S.LaneMask;

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  197     LaneMask &= ~SubRegMask;

lib/Target/Hexagon/RDFRegisters.cpp

  189     M &= ~SM;

utils/TableGen/CodeGenRegisters.cpp

 1530       CoveringLanes &= ~Mask;