reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/IR/Instructions.h

  832     return isFPOperation(getOperation());

lib/Bitcode/Writer/BitcodeWriter.cpp

 2978         getEncodedRMWOperation(cast<AtomicRMWInst>(I).getOperation()));

lib/CodeGen/AtomicExpandPass.cpp

  316         AtomicRMWInst::BinOp Op = RMWI->getOperation();
  576         return performAtomicOp(AI->getOperation(), Builder, Loaded,
  759     return performMaskedAtomicOp(AI->getOperation(), Builder, Loaded,
  777   AtomicRMWInst::BinOp Op = AI->getOperation();
  957   AtomicRMWInst::BinOp RMWOp = AI->getOperation();
 1321   AtomicRMWInst::BinOp Op = RMWI->getOperation();
 1436         return performAtomicOp(AI->getOperation(), Builder, Loaded,
 1570   ArrayRef<RTLIB::Libcall> Libcalls = GetRMWLibcall(I->getOperation());

lib/CodeGen/GlobalISel/IRTranslator.cpp

 1986   switch (I.getOperation()) {

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 4590   switch (I.getOperation()) {

lib/IR/AsmWriter.cpp

 3713     Out << ' ' << AtomicRMWInst::getOperationName(RMWI->getOperation());

lib/IR/Core.cpp

 3695   return mapToLLVMRMWBinOp(unwrap<AtomicRMWInst>(Inst)->getOperation());

lib/IR/Instruction.cpp

  432     return RMWI->getOperation() == cast<AtomicRMWInst>(I2)->getOperation() &&
  432     return RMWI->getOperation() == cast<AtomicRMWInst>(I2)->getOperation() &&

lib/IR/Instructions.cpp

 4162     new AtomicRMWInst(getOperation(), getOperand(0), getOperand(1),

lib/IR/Verifier.cpp

 3521   auto Op = RMWI.getOperation();

lib/Target/AArch64/AArch64ISelLowering.cpp

12148   if (AI->getOperation() == AtomicRMWInst::Nand) return AtomicExpansionKind::LLSC;

lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp

  116   AtomicRMWInst::BinOp Op = I.getOperation();

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 4676   switch (RMW->getOperation()) {

lib/Target/AMDGPU/SIISelLowering.cpp

10912   switch (RMW->getOperation()) {

lib/Target/RISCV/RISCVISelLowering.cpp

 2813       getIntrinsicForMaskedAtomicRMWBinOp(XLen, AI->getOperation()), Tys);
 2828   if (AI->getOperation() == AtomicRMWInst::Min ||
 2829       AI->getOperation() == AtomicRMWInst::Max) {

lib/Target/Sparc/SparcISelLowering.cpp

 1355   if (AI->getOperation() == AtomicRMWInst::Xchg &&

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  289   switch (AI->getOperation()) {

lib/Target/X86/X86ISelLowering.cpp

26493   AtomicRMWInst::BinOp Op = AI->getOperation();
26536     if (AI->getOperation() == AtomicRMWInst::Or && C->isZero() &&

lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp

   25     switch(RMWI.getOperation()) {
   38   switch(RMWI.getOperation()) {
   63     switch(RMWI.getOperation()) {
   75   switch(RMWI.getOperation()) {
  107       RMWI.getOperation() != AtomicRMWInst::Xchg) {
  119   if (RMWI.getOperation() == AtomicRMWInst::Xchg &&
  139       RMWI.getOperation() != AtomicRMWInst::Or) {
  144              RMWI.getOperation() != AtomicRMWInst::FAdd) {

lib/Transforms/Instrumentation/ThreadSanitizer.cpp

  664     FunctionCallee F = TsanAtomicRMW[RMWI->getOperation()][Idx];

lib/Transforms/Scalar/LowerAtomic.cpp

   50   switch (RMWI->getOperation()) {

lib/Transforms/Utils/FunctionComparator.cpp

  634     if (int Res = cmpNumbers(RMWI->getOperation(),
  635                              cast<AtomicRMWInst>(R)->getOperation()))