|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/CallingConvLower.h 552 Arg.Flags.setSecArgPass();
lib/CodeGen/CallingConvLower.cpp 105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
119 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
132 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 9242 MyFlags.Flags.setSplit();
9244 MyFlags.Flags.setOrigAlign(Align::None());
9246 MyFlags.Flags.setSplitEnd();
9254 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
lib/Target/AArch64/AArch64FastISel.cpp 3916 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
3916 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
3919 bool IsZExt = Outs[0].Flags.isZExt();
lib/Target/AArch64/AArch64ISelLowering.cpp 3766 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3788 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3864 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3985 if (Outs[i].Flags.isByVal()) {
3987 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3989 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
lib/Target/AMDGPU/SIISelLowering.cpp 2826 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2857 if (Outs[i].Flags.isByVal()) {
2859 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
2861 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
lib/Target/ARM/ARMFastISel.cpp 2150 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2150 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2151 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
lib/Target/ARM/ARMISelLowering.cpp 2066 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2135 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2642 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
lib/Target/BPF/BPFISelLowering.cpp 311 ISD::ArgFlagsTy Flags = Arg.Flags;
lib/Target/Hexagon/HexagonISelLowering.cpp 327 bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
383 ISD::ArgFlagsTy Flags = Outs[i].Flags;
lib/Target/Lanai/LanaiISelLowering.cpp 630 ISD::ArgFlagsTy Flags = Outs[I].Flags;
660 ISD::ArgFlagsTy Flags = Outs[I].Flags;
lib/Target/MSP430/MSP430ISelLowering.cpp 484 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
846 ISD::ArgFlagsTy Flags = Outs[i].Flags;
lib/Target/Mips/MipsCallLowering.cpp 402 Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
lib/Target/Mips/MipsFastISel.cpp 1759 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1759 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1760 bool IsZExt = Outs[0].Flags.isZExt();
lib/Target/Mips/MipsISelLowering.cpp 3130 ISD::ArgFlagsTy Flags = Outs[i].Flags;
lib/Target/NVPTX/NVPTXISelLowering.cpp 1315 if (!Outs[OIdx].Flags.isByVal()) {
1360 unsigned align = Outs[OIdx].Flags.getByValAlign();
1463 if (!Outs[OIdx].Flags.isByVal()) {
1522 StVal = DAG.getNode(Outs[OIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
1585 unsigned sz = Outs[OIdx].Flags.getByValSize();
1587 unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
2699 RetVal = DAG.getNode(Outs[i].Flags.isSExt() ? ISD::SIGN_EXTEND
lib/Target/PowerPC/PPCISelLowering.cpp 4569 if (Param.Flags.isNest()) continue;
4571 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
4669 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
5461 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5533 ISD::ArgFlagsTy Flags = Outs[RealArgIdx].Flags;
5732 if (Outs[i].Flags.isNest()) continue;
5733 if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags,
5752 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5876 ISD::ArgFlagsTy Flags = Outs[i].Flags;
6364 ISD::ArgFlagsTy Flags = Outs[i].Flags;
6459 ISD::ArgFlagsTy Flags = Outs[i].Flags;
lib/Target/RISCV/RISCVISelLowering.cpp 1652 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2052 auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
2079 if (Arg.Flags.isByVal())
2129 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2159 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2368 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
lib/Target/Sparc/SparcISelLowering.cpp 750 ISD::ArgFlagsTy Flags = Outs[i].Flags;
791 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
lib/Target/SystemZ/SystemZISelLowering.cpp 1452 if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
1452 if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 699 Outs[0].Flags.isSRet()) {
708 if (Out.Flags.isNest())
710 if (Out.Flags.isInAlloca())
712 if (Out.Flags.isInConsecutiveRegs())
714 if (Out.Flags.isInConsecutiveRegsLast())
716 if (Out.Flags.isByVal() && Out.Flags.getByValSize() != 0) {
716 if (Out.Flags.isByVal() && Out.Flags.getByValSize() != 0) {
718 int FI = MFI.CreateStackObject(Out.Flags.getByValSize(),
719 Out.Flags.getByValAlign(),
722 DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32);
725 Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getByValAlign(),
750 unsigned Align = std::max(Out.Flags.getOrigAlign(),
875 assert(!Out.Flags.isByVal() && "byval is not valid for return values");
876 assert(!Out.Flags.isNest() && "nest is not valid for return values");
878 if (Out.Flags.isInAlloca())
880 if (Out.Flags.isInConsecutiveRegs())
882 if (Out.Flags.isInConsecutiveRegsLast())
lib/Target/X86/X86FastISel.cpp 1228 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1228 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1234 if (Outs[0].Flags.isSExt())
1239 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
lib/Target/X86/X86ISelLowering.cpp 2926 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
3721 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3757 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
3945 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
4431 ISD::ArgFlagsTy Flags = Outs[i].Flags;