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References

include/llvm/CodeGen/CallingConvLower.h
  552       Arg.Flags.setSecArgPass();
lib/CodeGen/CallingConvLower.cpp
   92     ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
  167     ISD::ArgFlagsTy Flags = Ins[i].Flags;
lib/CodeGen/SelectionDAG/FastISel.cpp
 1162         MyFlags.Flags.setSExt();
 1164         MyFlags.Flags.setZExt();
 1166         MyFlags.Flags.setInReg();
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 9074         MyFlags.Flags = Flags;
 9079           MyFlags.Flags.setPointer();
 9080           MyFlags.Flags.setPointerAddrSpace(
 9084           MyFlags.Flags.setSExt();
 9086           MyFlags.Flags.setZExt();
 9088           MyFlags.Flags.setInReg();
 9102         MyFlags.Flags.setSwiftError();
 9712           MyFlags.Flags.setSplit();
 9715           MyFlags.Flags.setOrigAlign(Align::None());
 9717             MyFlags.Flags.setSplitEnd();
 9722         Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
 9792     if (Ins[i].Flags.isCopyElisionCandidate()) {
lib/Target/AArch64/AArch64ISelLowering.cpp
 3175         AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
 3184     if (Ins[i].Flags.isByVal()) {
 3188       int Size = Ins[i].Flags.getByValSize();
 3263           !Ins[i].Flags.isInConsecutiveRegs())
 3303     if (Subtarget->isTargetILP32() && Ins[i].Flags.isPointer())
 3350       if (Ins[I].Flags.isInReg()) {
lib/Target/AMDGPU/SIISelLowering.cpp
 1441   if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
 1441   if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
 1443     unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
 1509   if (Arg.Flags.isByVal()) {
 1510     unsigned Size = Arg.Flags.getByValSize();
 1577         !Arg->Flags.isInReg() && PSInputNum <= 15) {
 1583       if (Arg->Flags.isSplit()) {
 1584         while (!Arg->Flags.isSplitEnd()) {
 2139         DAG, VT, MemVT, DL, Chain, Offset, Align, Ins[i].Flags.isSExt(), &Ins[i]);
 2159       if (!Arg.Flags.isByVal())
 2173     if (Arg.Flags.isSRet()) {
lib/Target/ARC/ARCISelLowering.cpp
  514     const ArgDataPair ADP = {ArgIn, Ins[i].Flags};
lib/Target/ARM/ARMISelLowering.cpp
 3988     ISD::ArgFlagsTy Flags = Ins[Index].Flags;
 4074         if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
 4112           ISD::ArgFlagsTy Flags = Ins[index].Flags;
lib/Target/Hexagon/HexagonISelLowering.cpp
  720     ISD::ArgFlagsTy Flags = Ins[i].Flags;
lib/Target/MSP430/MSP430ISelLowering.cpp
  484     ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
  662       ISD::ArgFlagsTy Flags = Ins[i].Flags;
  692     if (Ins[i].Flags.isSRet()) {
lib/Target/Mips/MipsCCState.cpp
  156     if (Ins[i].Flags.isSRet()) {
lib/Target/Mips/MipsCallLowering.cpp
  402         Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
lib/Target/Mips/MipsISelLowering.cpp
 3503     ISD::ArgFlagsTy Flags = Ins[i].Flags;
 3588     if (Ins[i].Flags.isSRet()) {
lib/Target/NVPTX/NVPTXISelLowering.cpp
 2611               unsigned Extend = Ins[InsIdx].Flags.isSExt() ? ISD::SIGN_EXTEND
lib/Target/PowerPC/PPCISelLowering.cpp
 3738     if (Ins[i].Flags.isNest())
 3741     if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
 3765     ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
 4156       ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
 4208     ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
 4650   if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
 4727        ISD::ArgFlagsTy Flags = Ins[i].Flags;
lib/Target/RISCV/RISCVISelLowering.cpp
 1626     ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
lib/Target/Sparc/SparcISelLowering.cpp
  404     if (Ins[InIdx].Flags.isSRet()) {
 1296     CLI.Ins[0].Flags.setInReg();
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  816     assert(!In.Flags.isByVal() && "byval is not valid for return values");
  817     assert(!In.Flags.isNest() && "nest is not valid for return values");
  818     if (In.Flags.isInAlloca())
  820     if (In.Flags.isInConsecutiveRegs())
  822     if (In.Flags.isInConsecutiveRegsLast())
  904     if (In.Flags.isInAlloca())
  906     if (In.Flags.isNest())
  908     if (In.Flags.isInConsecutiveRegs())
  910     if (In.Flags.isInConsecutiveRegsLast())
lib/Target/X86/X86FastISel.cpp
 3560         ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
lib/Target/X86/X86ISelLowering.cpp
 2850         ((Is64Bit || Ins[InsIndex].Flags.isInReg()) && !Subtarget.hasSSE1())) {
 2940   const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
 3016   ISD::ArgFlagsTy Flags = Ins[i].Flags;
 3307     if (VA.getLocInfo() == CCValAssign::Indirect && !Ins[I].Flags.isByVal())
 3324     if (Ins[I].Flags.isSRet()) {
lib/Target/XCore/XCoreISelLowering.cpp
 1338     const ArgDataPair ADP = { ArgIn, Ins[i].Flags };