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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/ScheduleDAG.h 152 SUnit *getSUnit() const;
References
include/llvm/CodeGen/MachinePipeliner.h 248 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
334 if (Nodes.count(Succ.getSUnit()))
include/llvm/CodeGen/ScheduleDAG.h 433 if (Pred.getSUnit() == N)
441 if (Succ.getSUnit() == N)
631 return Node->Preds[Operand].getSUnit();
lib/CodeGen/AggressiveAntiDepBreaker.cpp 285 const SUnit *PredSU = P->getSUnit();
298 return (Next) ? Next->getSUnit() : nullptr;
852 SUnit *NextSU = Edge->getSUnit();
896 if (P->getSUnit() == NextSU ?
905 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
910 } else if ((P->getSUnit() != NextSU) &&
lib/CodeGen/CriticalAntiDepBreaker.cpp 151 const SUnit *PredSU = P->getSUnit();
556 const SUnit *NextSU = Edge->getSUnit();
580 if (P->getSUnit() == NextSU ?
lib/CodeGen/LatencyPriorityQueue.cpp 60 SUnit &Pred = *I->getSUnit();
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
95 AdjustPriorityOfUnscheduledPreds(I->getSUnit());
lib/CodeGen/MachinePipeliner.cpp 612 SUnit *SuccSU = SI.getSUnit();
821 MachineInstr *PMI = PI.getSUnit()->getInstr();
873 if (P->getSUnit() == DefSU)
876 Topo.RemovePred(&I, Deps[i].getSUnit());
882 if (P.getSUnit() == &I && P.getKind() == SDep::Order)
885 Topo.RemovePred(LastSU, Deps[i].getSUnit());
1130 SUnit *TargetSU = D.getSUnit();
1152 int N = SI.getSUnit()->NodeNum;
1163 if (SI.getSUnit()->isBoundaryNode() || SI.isArtificial() ||
1164 (SI.getKind() == SDep::Anti && !SI.getSUnit()->getInstr()->isPHI()))
1166 int N = SI.getSUnit()->NodeNum;
1178 if (PI.getKind() == SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) {
1179 int N = PI.getSUnit()->NodeNum;
1299 SUnit *TmpSU = Dep.getSUnit();
1322 SUnit *TmpSU = Dep.getSUnit();
1386 SUnit *pred = IP->getSUnit();
1410 SUnit *succ = IS->getSUnit();
1453 if (S && S->count(PI->getSUnit()) == 0)
1457 if (NodeOrder.count(PI->getSUnit()) == 0)
1458 Preds.insert(PI->getSUnit());
1466 if (S && S->count(IS->getSUnit()) == 0)
1468 if (NodeOrder.count(IS->getSUnit()) == 0)
1469 Preds.insert(IS->getSUnit());
1486 if (S && S->count(SI->getSUnit()) == 0)
1490 if (NodeOrder.count(SI->getSUnit()) == 0)
1491 Succs.insert(SI->getSUnit());
1498 if (S && S->count(PI->getSUnit()) == 0)
1500 if (NodeOrder.count(PI->getSUnit()) == 0)
1501 Succs.insert(PI->getSUnit());
1523 FoundPath |= computePath(SI.getSUnit(), Path, DestNodes, Exclude, Visited);
1527 computePath(PI.getSUnit(), Path, DestNodes, Exclude, Visited);
1743 SUnit *Successor = SI.getSUnit();
1748 SUnit *Predecessor = PI.getSUnit();
1872 if (Nodes.count(I.getSUnit()) == 0)
1874 if (NodeOrder.count(I.getSUnit()) != 0)
1878 R.insert(I.getSUnit());
1884 if (Nodes.count(I.getSUnit()) == 0)
1886 if (NodeOrder.count(I.getSUnit()) != 0)
1888 R.insert(I.getSUnit());
1923 if (Nodes.count(I.getSUnit()) == 0)
1925 if (NodeOrder.count(I.getSUnit()) != 0)
1927 R.insert(I.getSUnit());
1933 if (Nodes.count(I.getSUnit()) == 0)
1935 if (NodeOrder.count(I.getSUnit()) != 0)
1937 R.insert(I.getSUnit());
2217 MachineInstr *DI = Dep.getSUnit()->getInstr();
2346 SUnit *PrevSU = Cur.getSUnit();
2369 SUnit *SuccSU = Cur.getSUnit();
2389 if (DAG->isBackedge(SU, P) && P.getSUnit()->getInstr()->isPHI())
2390 for (auto &S : P.getSUnit()->Succs)
2391 if (S.getKind() == SDep::Data && S.getSUnit()->getInstr()->isPHI())
2392 return P.getSUnit();
2412 if (Dep.getSUnit() == I) {
2415 DAG->getDistance(Dep.getSUnit(), SU, Dep) * II;
2423 DAG->getDistance(SU, Dep.getSUnit(), Dep) * II;
2430 if (BE && Dep.getSUnit() == BE && !SU->getInstr()->isPHI() &&
2435 if (SU->Succs[i].getSUnit() == I) {
2439 DAG->getDistance(SU, Dep.getSUnit(), Dep) * II;
2447 DAG->getDistance(Dep.getSUnit(), SU, Dep) * II;
2527 if (S.getSUnit() != *I)
2544 if (P.getSUnit() != *I)
2652 if (stageScheduled(SI.getSUnit()) != StageDef)
2704 SUnit *PredSU = PredEdge.getSUnit();
2715 SUnit *SuccSU = SuccEdge.getSUnit();
lib/CodeGen/MachineScheduler.cpp 618 SUnit *SuccSU = SuccEdge->getSUnit();
655 SUnit *PredSU = PredEdge->getSUnit();
1584 if (Succ.getSUnit() == SUb)
1586 LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum
1588 DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial));
1610 ChainPredID = Pred.getSUnit()->NodeNum;
1773 if (Succ.getSUnit() == GlobalSU)
1775 if (!DAG->canAddEdge(GlobalSU, Succ.getSUnit()))
1777 LocalUses.push_back(Succ.getSUnit());
1788 if (Pred.getSUnit() == FirstLocalSU)
1790 if (!DAG->canAddEdge(FirstLocalSU, Pred.getSUnit()))
1792 GlobalUses.push_back(Pred.getSUnit());
3265 SUnit *DepSU = Dep.getSUnit();
3272 DAG->dumpNode(*Dep.getSUnit()));
lib/CodeGen/MacroFusion.cpp 61 if (SI.getSUnit() == &SecondSU)
65 if (SI.getSUnit() == &FirstSU)
78 SUnit *SU = SI.getSUnit();
91 SUnit *SU = SI.getSUnit();
160 SUnit &DepSU = *Dep.getSUnit();
lib/CodeGen/PostRASchedulerList.cpp 454 SUnit *SuccSU = SuccEdge->getSUnit();
lib/CodeGen/ScheduleDAG.cpp 112 if (!Required && PredDep.getSUnit() == D.getSUnit())
112 if (!Required && PredDep.getSUnit() == D.getSUnit())
118 SUnit *PredSU = PredDep.getSUnit();
136 SUnit *N = D.getSUnit();
183 SUnit *N = D.getSUnit();
225 SUnit *SuccSU = SuccDep.getSUnit();
240 SUnit *PredSU = PredDep.getSUnit();
273 SUnit *PredSU = PredDep.getSUnit();
304 SUnit *SuccSU = SuccDep.getSUnit();
330 unsigned MaxDepth = BestI->getSUnit()->getDepth();
333 if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth)
370 dumpNodeName(*Dep.getSUnit());
380 dumpNodeName(*Dep.getSUnit());
501 SUnit *SU = PredDep.getSUnit();
516 assert(Node2Index[SU.NodeNum] > Node2Index[PD.getSUnit()->NodeNum] &&
582 unsigned s = SuccDep.getSUnit()->NodeNum;
592 WorkList.push_back(SuccDep.getSUnit());
623 const SUnit *Succ = SU->Succs[I].getSUnit();
657 const SUnit *Pred = SU->Preds[I].getSUnit();
711 IsReachable(SU, PredDep.getSUnit()))
lib/CodeGen/ScheduleDAGInstrs.cpp 1199 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
1201 Topo.AddPredQueued(SuccSU, PredDep.getSUnit());
1277 unsigned PredNum = PredDep.getSUnit()->NodeNum;
1305 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount;
1311 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ));
1358 const SUnit *PredSU = PredDep.getSUnit();
1434 !SuccDep.getSUnit()->isBoundaryNode())
1461 || PredDep.getSUnit()->isBoundaryNode()) {
1465 if (Impl.isVisited(PredDep.getSUnit())) {
1469 Impl.visitPreorder(PredDep.getSUnit());
1470 DFS.follow(PredDep.getSUnit());
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 73 SUnit *PredSU = Pred.getSUnit();
111 SUnit *SuccSU = Succ.getSUnit();
213 SUnit &PredSU = *Pred.getSUnit();
230 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU)
274 if (Succ.getSUnit() == SU)
499 if (Pred.isCtrl() || (Pred.getSUnit()->NumRegDefsLeft == 0))
501 --Pred.getSUnit()->NumRegDefsLeft;
514 adjustPriorityOfUnscheduledPreds(Succ.getSUnit());
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 140 SUnit *PredSU = PredEdge->getSUnit();
171 LiveRegDefs[Pred.getReg()] = Pred.getSUnit();
194 if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) {
285 else if (Pred.getSUnit()->getNode() &&
286 Pred.getSUnit()->getNode()->isOperandOf(LoadNode))
298 if (ChainPred.getSUnit()) {
317 SUnit *SuccDep = D.getSUnit();
325 SUnit *SuccDep = D.getSUnit();
362 SUnit *SuccSU = Succ.getSUnit();
398 SUnit *SuccSU = Succ.getSUnit();
476 CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs,
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 226 Topo.AddPredQueued(SU, D.getSUnit());
234 Topo.AddPred(SU, D.getSUnit());
242 Topo.RemovePred(SU, D.getSUnit());
399 SUnit *PredSU = PredEdge->getSUnit();
564 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) &&
566 LiveRegDefs[Pred.getReg()] = Pred.getSUnit();
821 SUnit *PredSU = PredEdge->getSUnit();
843 assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() &&
899 LiveRegGens[Reg] = Succ.getSUnit();
902 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight())
903 LiveRegGens[Reg] = Succ2.getSUnit();
1065 else if (isOperandOf(Pred.getSUnit(), LoadNode))
1093 SUnit *SuccDep = D.getSUnit();
1104 SUnit *SuccDep = D.getSUnit();
1201 SUnit *SuccSU = Succ.getSUnit();
1240 SUnit *SuccSU = Succ.getSUnit();
1357 CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(),
1963 SUnit *PredSU = Pred.getSUnit();
1986 SUnit *PredSU = Pred.getSUnit();
2090 SUnit *PredSU = Pred.getSUnit();
2139 SUnit *PredSU = Pred.getSUnit();
2182 SUnit *PredSU = Pred.getSUnit();
2264 SUnit *PredSU = Pred.getSUnit();
2331 unsigned Height = Succ.getSUnit()->getHeight();
2334 if (Succ.getSUnit()->getNode() &&
2335 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg)
2336 Height = closestSucc(Succ.getSUnit())+1;
2360 const SUnit *PredSU = Pred.getSUnit();
2382 const SUnit *SuccSU = Succ.getSUnit();
2419 Pred.getSUnit()->isVRegCycle = true;
2431 SUnit *PredSU = Pred.getSUnit();
2435 Pred.getSUnit()->isVRegCycle = false;
2449 if (Pred.getSUnit()->isVRegCycle &&
2450 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2848 SUnit *SuccSU = Succ.getSUnit();
2855 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2864 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit()))
2961 if (Pred.isCtrl() && Pred.getSUnit()) {
2963 SDNode *PredND = Pred.getSUnit()->getNode();
2986 PredSU = Pred.getSUnit();
3008 SUnit *PredSuccSU = PredSucc.getSUnit();
3032 SUnit *SuccSU = Edge.getSUnit();
3079 SUnit *SuccSU = Succ.getSUnit();
3095 SuccSU = SuccSU->Succs.front().getSUnit();
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 792 if (I->getSUnit()->CopyDstRC) {
794 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp 114 SUnit *SuccSU = D.getSUnit();
lib/Target/AMDGPU/AMDGPUSubtarget.cpp 747 if (SI.getSUnit() != SUa)
748 SUa->addPred(SDep(SI.getSUnit(), SDep::Artificial));
753 if (SI.getSUnit() != &SU)
754 SI.getSUnit()->addPred(SDep(&SU, SDep::Artificial));
789 const SUnit *SU = SI.getSUnit();
802 if (SI.getSUnit() != SU && !Visited.count(SI.getSUnit()))
802 if (SI.getSUnit() != SU && !Visited.count(SI.getSUnit()))
803 Preds.push_back(SI.getSUnit());
828 SUnit *SUv = SI.getSUnit();
834 SUnit *Succ = SI.getSUnit();
lib/Target/AMDGPU/GCNILPSched.cpp 67 SUnit *PredSU = Pred.getSUnit();
111 unsigned Height = Succ.getSUnit()->getHeight();
278 auto PredSU = PredEdge.getSUnit();
lib/Target/AMDGPU/GCNMinRegStrategy.cpp 96 for (auto PDep : SDep.getSUnit()->Preds) {
97 auto PSU = PDep.getSUnit();
186 if (S.getSUnit()->isBoundaryNode() || isScheduled(S.getSUnit()) ||
186 if (S.getSUnit()->isBoundaryNode() || isScheduled(S.getSUnit()) ||
189 for (const auto &P : S.getSUnit()->Preds) {
190 auto PSU = P.getSUnit();
202 if (!P.getSUnit()->isBoundaryNode() && !isScheduled(P.getSUnit()) &&
202 if (!P.getSUnit()->isBoundaryNode() && !isScheduled(P.getSUnit()) &&
203 Set.insert(P.getSUnit()).second)
204 Worklist.push_back(P.getSUnit());
222 auto SuccSU = S.getSUnit();
lib/Target/AMDGPU/R600Packetizer.cpp 196 if (Dep.getSUnit() != SUI)
lib/Target/AMDGPU/SIMachineScheduler.cpp 444 if (BC->isSUInBlock(Succ.getSUnit(), ID))
454 SUnit *SuccSU = SuccEdge->getSUnit();
464 SUnit *SuccSU = SuccEdge->getSUnit();
485 SUnit *SuccSU = Succ.getSUnit();
518 NodeNum2Index.find(Succ.getSUnit()->NodeNum);
672 if (PredDep.getSUnit() == &FromSU &&
828 SUnit *Pred = PredDep.getSUnit();
870 SUnit *Succ = SuccDep.getSUnit();
954 SUnit *Succ = SuccDep.getSUnit();
1024 SUnit *Succ = SuccDep.getSUnit();
1045 SUnit *Succ = SuccDep.getSUnit();
1066 SUnit *Succ = SuccDep.getSUnit();
1098 SUnit *Succ = SuccDep.getSUnit();
1127 SUnit *Succ = SuccDep.getSUnit();
1244 SUnit *Succ = SuccDep.getSUnit();
1252 SUnit *Pred = PredDep.getSUnit();
1841 SUnit *Pred = PredDep.getSUnit();
1876 SUnit *Succ = SuccDep.getSUnit();
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 145 S.getSUnit()->NumPredsLeft == 1) {
146 UsesDotCur = S.getSUnit();
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) &&
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) {
162 PrefVectorStoreNew = S.getSUnit();
lib/Target/Hexagon/HexagonMachineScheduler.cpp 86 if (S.getSUnit() == SUu && S.getLatency() > 0)
293 unsigned PredReadyCycle = PI.getSUnit()->TopReadyCycle;
312 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
527 if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2))
527 if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2))
542 if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2))
542 if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2))
647 if (isSingleUnscheduledPred(SI.getSUnit(), SU))
653 if (isSingleUnscheduledSucc(PI.getSUnit(), SU))
707 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() &&
709 Top.ResourceModel->isInPacket(PI.getSUnit())) {
716 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() &&
718 Bot.ResourceModel->isInPacket(SI.getSUnit())) {
734 Top.ResourceModel->isInPacket(PI.getSUnit())) {
742 Bot.ResourceModel->isInPacket(SI.getSUnit())) {
lib/Target/Hexagon/HexagonSubtarget.cpp 155 MachineInstr &MI2 = *SI.getSUnit()->getInstr();
162 for (SDep &PI : SI.getSUnit()->Preds) {
163 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
166 SI.getSUnit()->setDepthDirty();
348 MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
421 if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
460 if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
477 !I.getSUnit()->getInstr()->isPseudo())
478 return I.getSUnit();
555 if (ExclSrc.count(I.getSUnit()) == 0 &&
556 isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
557 changeLatency(I.getSUnit(), DstBest, 0);
563 if (ExclDst.count(I.getSUnit()) == 0 &&
564 isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
565 changeLatency(SrcBest, I.getSUnit(), 0);
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 929 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti &&
997 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
1399 if (SUJ->Succs[i].getSUnit() != SUI)
1861 if (Pred.getSUnit() == SUJ)
1872 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
lib/Target/PowerPC/PPCHazardRecognizers.cpp 39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
47 if (SU->Preds[i].getSUnit() == CurGroup[j])
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
73 if (SU->Preds[i].getSUnit() == CurGroup[j])