reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
158 Kind getKind() const;
246 if (Dep.getKind() != SDep::Anti) 258 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)include/llvm/CodeGen/ScheduleDAG.h
162 return getKind() != Data; 169 return getKind() == Order && (Contents.OrdKind == MayAliasMem 175 return getKind() == Order && Contents.OrdKind == Barrier; 187 return getKind() == Order && Contents.OrdKind == MustAliasMem; 195 return getKind() == Order && Contents.OrdKind >= Weak; 201 return getKind() == Order && Contents.OrdKind == Artificial; 207 return getKind() == Order && Contents.OrdKind == Cluster; 212 return getKind() == Data && Contents.Reg != 0; 219 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 219 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 219 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 229 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 229 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 229 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 231 assert((getKind() != Anti || Reg != 0) && 233 assert((getKind() != Output || Reg != 0) &&lib/CodeGen/AggressiveAntiDepBreaker.cpp
269 if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) { 269 if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) { 291 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 854 if ((Edge->getKind() != SDep::Anti) && 855 (Edge->getKind() != SDep::Output)) continue; 897 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 898 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) { 905 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) && 906 (P->getKind() != SDep::Output)) { 911 (P->getKind() == SDep::Data) && 930 SDep::Kind K = S.getKind();lib/CodeGen/CriticalAntiDepBreaker.cpp
157 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) { 559 if (Edge->getKind() == SDep::Anti) { 581 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) : 582 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {lib/CodeGen/MachinePipeliner.cpp
613 if (SI.getKind() == SDep::Order) { 822 if (PMI->isPHI() && PI.getKind() == SDep::Order) { 882 if (P.getSUnit() == &I && P.getKind() == SDep::Order) 1119 if (IP->getKind() != SDep::Anti) 1151 if (SI.getKind() == SDep::Output) { 1164 (SI.getKind() == SDep::Anti && !SI.getSUnit()->getInstr()->isPHI())) 1178 if (PI.getKind() == SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) { 1301 SDep::Kind DepKind = Dep.getKind(); 1319 if (Dep.getKind() != SDep::Data) 1354 return D.getKind() == SDep::Anti && isPred; 1464 if (IS->getKind() != SDep::Anti) 1496 if (PI->getKind() != SDep::Anti) 1525 if (PI.getKind() == SDep::Anti) 1882 if (I.getKind() != SDep::Anti) 1931 if (I.getKind() != SDep::Anti) 2206 if ((Dep.getKind() != SDep::Order && Dep.getKind() != SDep::Output) || 2206 if ((Dep.getKind() != SDep::Order && Dep.getKind() != SDep::Output) || 2213 if (Dep.getKind() == SDep::Output) 2354 if (PI.getKind() == SDep::Order || Dep.getKind() == SDep::Output) 2354 if (PI.getKind() == SDep::Order || Dep.getKind() == SDep::Output) 2377 if (SI.getKind() == SDep::Order || Dep.getKind() == SDep::Output) 2377 if (SI.getKind() == SDep::Order || Dep.getKind() == SDep::Output) 2391 if (S.getKind() == SDep::Data && S.getSUnit()->getInstr()->isPHI()) 2529 if (S.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) { 2537 else if (S.getKind() == SDep::Anti && stageScheduled(*I) == StageInst1) { 2546 if (P.getKind() == SDep::Order && stageScheduled(*I) == StageInst1) {lib/CodeGen/MachineScheduler.cpp
1771 if (Succ.getKind() != SDep::Data || Succ.getReg() != LocalReg) 1786 if (Pred.getKind() != SDep::Anti || Pred.getReg() != GlobalReg) 3262 if (Dep.getKind() != SDep::Data ||lib/CodeGen/MacroFusion.cpp
36 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output; 36 return Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output;lib/CodeGen/ScheduleDAG.cpp
76 switch (getKind()) { 83 switch (getKind()) { 138 if (D.getKind() == SDep::Data) { 189 if (P.getKind() == SDep::Data) { 333 if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth)lib/CodeGen/ScheduleDAGInstrs.cpp
1275 if (PredDep.getKind() != SDep::Data) 1355 assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges"); 1367 if (SuccDep.getKind() == SDep::Data) { 1433 if (SuccDep.getKind() == SDep::Data && 1460 if (PredDep.getKind() != SDep::Datalib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
648 if (dep.getKind() != SDep::Data)
lib/Target/AMDGPU/GCNMinRegStrategy.cpp 187 S.getKind() != SDep::Data)
lib/Target/AMDGPU/R600Packetizer.cpp198 if (Dep.getKind() == SDep::Anti) 200 if (Dep.getKind() == SDep::Output)lib/Target/AMDGPU/SIMachineScheduler.cpp
673 PredDep.getKind() == llvm::SDep::Data)
lib/Target/Hexagon/HexagonSubtarget.cpp134 if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF) 153 if (SI.getKind() != SDep::Order || SI.getLatency() != 0) 163 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
526 if (PI.getKind() != SDep::Anti && 527 (PI.getKind() != SDep::Data || PI.getReg() != Reg)) 929 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti && 997 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data && 1402 SDep::Kind DepType = SUJ->Succs[i].getKind();