|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachinePipeliner.h 248 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
248 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
258 if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)
include/llvm/CodeGen/ScheduleDAG.h 387 ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0);
387 ((SU->getInstr()->mayStore() && this->getInstr()->mayLoad()) ? 1 : 0);
582 if (SU->isInstr()) return &SU->getInstr()->getDesc();
include/llvm/CodeGen/ScheduleDAGInstrs.h 267 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
lib/CodeGen/AggressiveAntiDepBreaker.cpp 775 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
794 CriticalPathMI = CriticalPathSU->getInstr();
841 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
lib/CodeGen/CriticalAntiDepBreaker.cpp 456 MISUnitMap[SU->getInstr()] = SU;
478 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
589 CriticalPathMI = CriticalPathSU->getInstr();
lib/CodeGen/DFAPacketizer.cpp 247 MIToSUnit[SU.getInstr()] = &SU;
lib/CodeGen/MachinePipeliner.cpp 536 OrderedInsts.push_back(SU->getInstr());
537 Cycles[SU->getInstr()] = Cycle;
538 Stages[SU->getInstr()] = Schedule.stageScheduled(SU);
665 MachineInstr &MI = *SU.getInstr();
690 MachineInstr &LdMI = *Load->getInstr();
765 MachineInstr *MI = I.getInstr();
821 MachineInstr *PMI = PI.getSUnit()->getInstr();
823 if (I.getInstr()->isPHI()) {
846 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase,
851 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg();
1164 (SI.getKind() == SDep::Anti && !SI.getSUnit()->getInstr()->isPHI()))
1175 if (!SUnits[i].getInstr()->mayStore() ||
1178 if (PI.getKind() == SDep::Order && PI.getSUnit()->getInstr()->mayLoad()) {
1290 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence())
1290 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence())
1300 MachineInstr *TmpMI = TmpSU->getInstr();
1323 MachineInstr *TmpMI = TmpSU->getInstr();
1551 const MachineInstr *MI = SU->getInstr();
1565 for (const MachineOperand &MO : SU->getInstr()->operands())
1605 MachineBasicBlock::const_iterator CurInstI = SU->getInstr();
1610 RecRPTracker.getMaxUpwardPressureDelta(SU->getInstr(), nullptr, RPDelta,
1993 SU->getInstr()->dump();
2016 if (SU->getInstr()->isPHI())
2216 MachineInstr *SI = Source->getInstr();
2217 MachineInstr *DI = Dep.getSUnit()->getInstr();
2308 if (ST.getInstrInfo()->isZeroCost((*I)->getInstr()->getOpcode()))
2310 assert(ProcItinResources.canReserveResources(*(*I)->getInstr()) &&
2312 ProcItinResources.reserveResources(*(*I)->getInstr());
2315 if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()) ||
2316 ProcItinResources.canReserveResources(*SU->getInstr())) {
2319 SU->getInstr()->dump();
2332 SU->getInstr()->dump();
2389 if (DAG->isBackedge(SU, P) && P.getSUnit()->getInstr()->isPHI())
2391 if (S.getKind() == SDep::Data && S.getSUnit()->getInstr()->isPHI())
2430 if (BE && Dep.getSUnit() == BE && !SU->getInstr()->isPHI() &&
2461 MachineInstr *MI = SU->getInstr();
2485 (*I)->getInstr()->readsWritesVirtualRegister(Reg);
2517 isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {
2602 if (UseSU->getInstr()->isPHI())
2707 if (!PredSU->getInstr()->isPHI() && PredIndex < Index) {
2723 if (!SuccSU->getInstr()->isPHI() && SuccIndex < Index) {
2730 if (PredBefore && SuccBefore && !SU->getInstr()->isPHI()) {
2764 MachineInstr *MI = SU->getInstr();
2832 SSD->applyInstrChange(SU->getInstr(), *this);
2842 if (SU->getInstr()->isPHI())
2848 if (!SU->getInstr()->isPHI())
2864 os << " SU(" << I->NodeNum << ") " << *(I->getInstr());
2878 CI->getInstr()->print(os);
lib/CodeGen/MachineScheduler.cpp 779 MachineInstr *MI = SU->getInstr();
929 const MachineInstr &MI = *SU.getInstr();
1120 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
1149 LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
1154 << *SU->getInstr();
1165 if (EntrySU.getInstr() != nullptr)
1174 if (SchedModel.mustBeginGroup(SU.getInstr()) &&
1175 SchedModel.mustEndGroup(SU.getInstr()))
1181 if (ExitSU.getInstr() != nullptr)
1346 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr()));
1388 MachineInstr *MI = SU->getInstr();
1562 if (TII->getMemOperandWithOffset(*SU->getInstr(), BaseOp, Offset, TRI))
1603 if ((IsLoad && !SU.getInstr()->mayLoad()) ||
1604 (!IsLoad && !SU.getInstr()->mayStore()))
1688 MachineInstr *Copy = CopySU->getInstr();
1824 if (!SU.getInstr()->isCopy())
1894 RemIssueCount += SchedModel->getNumMicroOps(SU.getInstr(), SC)
2000 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
2003 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
2008 ((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) ||
2009 (!isTop() && SchedModel->mustEndGroup(SU->getInstr())))) {
2089 assert(SU->getInstr() && "Scheduled SUnit must have instr");
2213 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
2325 if ((isTop() && SchedModel->mustEndGroup(SU->getInstr())) ||
2326 (!isTop() && SchedModel->mustBeginGroup(SU->getInstr()))) {
2912 const MachineInstr *MI = SU->getInstr();
2957 Cand.SU->getInstr(),
2964 Cand.SU->getInstr(),
2971 Cand.SU->getInstr(),
3249 << *SU->getInstr());
3254 MachineBasicBlock::iterator InsertPos = SU->getInstr();
3268 MachineInstr *Copy = DepSU->getInstr();
3442 << *SU->getInstr());
3539 << "Scheduling " << *SU->getInstr());
lib/CodeGen/MacroFusion.cpp 71 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - "
72 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';);
138 if (DAG->ExitSU.getInstr())
146 const MachineInstr &AnchorMI = *AnchorSU.getInstr();
164 const MachineInstr *DepMI = DepSU.getInstr();
lib/CodeGen/PostRASchedulerList.cpp 681 BB->splice(RegionEnd, BB, SU->getInstr());
lib/CodeGen/ScheduleDAGInstrs.cpp 230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
238 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
262 RegUse = UseSU->getInstr();
265 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr);
270 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
285 MachineInstr *MI = SU->getInstr();
308 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
314 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
389 MachineInstr *MI = SU->getInstr();
438 MachineInstr *Use = UseSU->getInstr();
484 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
509 const MachineInstr *MI = SU->getInstr();
541 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
541 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
576 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
1158 SU.getInstr()->dump();
1164 if (EntrySU.getInstr() != nullptr)
1168 if (ExitSU.getInstr() != nullptr)
1181 SU->getInstr()->print(oss, /*SkipOpers=*/true);
1255 SU->getInstr()->isTransient() ? 0 : 1;
1266 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
lib/Target/AMDGPU/AMDGPUSubtarget.cpp 729 MachineInstr &MI2 = *SU.getInstr();
739 MachineInstr &MI1 = *SUa->getInstr();
772 const MachineInstr *MI = SU->getInstr();
777 const MachineInstr *MI = SU->getInstr();
860 MachineInstr &MAI = *SU.getInstr();
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 54 EmitInstruction(SU->getInstr());
133 MachineInstr *MI = SU->getInstr();
233 return PreEmitNoopsCommon(SU->getInstr());
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 52 return SU->getInstr();
55 return SU.getInstr();
346 Res.push_back(SU->getInstr());
348 return P.second == SU->getInstr();
lib/Target/AMDGPU/GCNSchedStrategy.cpp 78 TempTracker.getDownwardPressure(SU->getInstr(), Pressure, MaxPressure);
82 TempTracker.getUpwardPressure(SU->getInstr(), Pressure, MaxPressure);
308 << *SU->getInstr());
lib/Target/AMDGPU/R600MachineScheduler.cpp 161 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
162 E = SU->getInstr()->operands_end(); It != E; ++It) {
195 if (isPhysicalRegCopy(SU->getInstr())) {
220 MachineInstr *MI = SU->getInstr();
294 int Opcode = SU->getInstr()->getOpcode();
323 InstructionsGroupCandidate.push_back(SU->getInstr());
325 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) {
394 AssignSlot(UnslotedSU->getInstr(), Slot);
443 InstructionsGroupCandidate.push_back(SU->getInstr());
lib/Target/AMDGPU/R600Packetizer.cpp 183 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
183 MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
lib/Target/AMDGPU/SIMachineScheduler.cpp 271 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure);
338 RPTracker.setPos(SU->getInstr());
419 TopRPTracker.setPos(SU->getInstr());
1153 if (SIInstrInfo::isEXP(*SU.getInstr())) {
1177 if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr()))
1362 MachineInstr *MI = SU->getInstr();
1391 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr());
1391 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr());
1842 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) {
1852 if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
1873 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) {
1879 if (SITII->isLowLatencyInstruction(*Succ->getInstr())) {
1961 if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
1963 if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,
1966 } else if (SITII->isHighLatencyInstruction(*SU->getInstr()))
2038 << *SU->getInstr());
lib/Target/ARM/ARMHazardRecognizer.cpp 37 MachineInstr *MI = SU->getInstr();
82 MachineInstr *MI = SU->getInstr();
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 40 MachineInstr *MI = SU->getInstr();
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad())
109 MachineInstr *MI = SU->getInstr();
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) &&
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) {
lib/Target/Hexagon/HexagonMachineScheduler.cpp 74 if (QII.mayBeCurLoad(*SUd->getInstr()))
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
98 if (!SU || !SU->getInstr())
103 switch (SU->getInstr()->getOpcode()) {
105 if (!ResourcesModel->canReserveResources(*SU->getInstr()))
119 MachineBasicBlock *MBB = SU->getInstr()->getParent();
157 switch (SU->getInstr()->getOpcode()) {
159 ResourcesModel->reserveResources(*SU->getInstr());
181 LLVM_DEBUG(Packet[i]->getInstr()->dump());
308 assert(SU->getInstr() && "Scheduled SUnit must have instr");
340 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
407 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
505 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
513 (*I)->getInstr()->dump();
691 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
707 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() &&
716 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() &&
779 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
lib/Target/Hexagon/HexagonSubtarget.cpp 146 MachineInstr &MI1 = *SU.getInstr();
155 MachineInstr &MI2 = *SI.getSUnit()->getInstr();
183 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
187 unsigned Type = HII.getType(*Inst2.getInstr());
207 if (DAG->SUnits[su].getInstr()->isCall())
210 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
231 const MachineInstr *MI = DAG->SUnits[su].getInstr();
273 MachineInstr &L0 = *S0.getInstr();
286 MachineInstr &L1 = *S1.getInstr();
321 MachineInstr *SrcInst = Src->getInstr();
322 MachineInstr *DstInst = Dst->getInstr();
348 MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
419 MachineInstr *SrcI = Src->getInstr();
431 MachineInstr *DstI = Dst->getInstr();
477 !I.getSUnit()->getInstr()->isPseudo())
489 MachineInstr &SrcInst = *Src->getInstr();
490 MachineInstr &DstInst = *Dst->getInstr();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 415 if (PacketSU->getInstr()->isInlineAsm())
509 assert(SUI->getInstr() && SUJ->getInstr());
509 assert(SUI->getInstr() && SUJ->getInstr());
510 MachineInstr &MI = *SUI->getInstr();
511 MachineInstr &MJ = *SUJ->getInstr();
666 if (PacketSU->getInstr()->mayStore())
752 MachineInstr &TempMI = *TempSU->getInstr();
765 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
819 MachineInstr &PacketMI = *PacketSU->getInstr();
852 const MachineInstr &PI = *PacketSU->getInstr();
1311 assert(SUI->getInstr() && SUJ->getInstr());
1311 assert(SUI->getInstr() && SUJ->getInstr());
1312 MachineInstr &I = *SUI->getInstr();
1313 MachineInstr &J = *SUJ->getInstr();
1622 assert(SUI->getInstr() && SUJ->getInstr());
1622 assert(SUI->getInstr() && SUJ->getInstr());
1623 MachineInstr &I = *SUI->getInstr();
1624 MachineInstr &J = *SUJ->getInstr();
lib/Target/PowerPC/PPCHazardRecognizers.cpp 328 MachineInstr *MI = SU->getInstr();
386 MachineInstr *MI = SU->getInstr();
lib/Target/PowerPC/PPCMachineScheduler.cpp 31 if (isADDIInstr(*FirstCand.SU->getInstr()) &&
32 SecondCand.SU->getInstr()->mayLoad()) {
36 if (FirstCand.SU->getInstr()->mayLoad() &&
37 isADDIInstr(*SecondCand.SU->getInstr())) {
lib/Target/SystemZ/SystemZHazardRecognizer.cpp 105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))
169 OS << TII->getName(SU->getInstr()->getOpcode());
204 if (has4RegOps(SU->getInstr()))
285 LastEmittedMI = SU->getInstr();
291 LastEmittedMI = SU->getInstr();
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr());
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr()))
lib/Target/SystemZ/SystemZHazardRecognizer.h 123 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr());