|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/CodeGen/BranchFolding.cpp 880 MO.setIsUndef(false);
lib/CodeGen/DetectDeadLanes.cpp 554 MO.setIsUndef();
558 MO.setIsUndef();
lib/CodeGen/InlineSpiller.cpp 560 MO.setIsUndef();
lib/CodeGen/MachineInstr.cpp 1928 MO.setIsUndef(IsUndef);
lib/CodeGen/MachineOperand.cpp 92 setIsUndef(false);
lib/CodeGen/PeepholeOptimizer.cpp 591 Copy->getOperand(0).setIsUndef();
1241 NewCopy->getOperand(0).setIsUndef();
lib/CodeGen/ProcessImplicitDefs.cpp 82 MO.setIsUndef();
110 MO.setIsUndef();
lib/CodeGen/RegisterCoalescer.cpp 1303 DefMO.setIsUndef(false); // Only subregs can have def+undef.
1368 NewMI.getOperand(0).setIsUndef(false);
1460 NewMI.getOperand(0).setIsUndef();
1608 MO.setIsUndef(true);
1619 MO.setIsUndef(true);
1640 MO.setIsUndef(true);
1701 MO.setIsUndef(!Reads);
2946 MO.setIsUndef(false);
lib/CodeGen/RenameIndependentSubregs.cpp 356 MO.setIsUndef();
lib/CodeGen/ScheduleDAGInstrs.cpp 416 MO.setIsUndef(false);
lib/CodeGen/TargetInstrInfo.cpp 226 CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
227 CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
lib/CodeGen/TwoAddressInstructionPass.cpp 1769 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1845 CopyMI->getOperand(0).setIsUndef(true);
lib/CodeGen/VirtRegMap.cpp 547 MO.setIsUndef(true);
558 MO.setIsUndef(false);
lib/Target/AArch64/AArch64InstrInfo.cpp 3345 LoadDst.setIsUndef();
lib/Target/AMDGPU/GCNDPPCombine.cpp 547 S.first->getOperand(S.second.pop_back_val()).setIsUndef(true);
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 393 Op.setIsUndef(false);
lib/Target/AMDGPU/GCNSchedStrategy.cpp 411 Op.setIsUndef(false);
lib/Target/AMDGPU/SIFoldOperands.cpp 303 Old.setIsUndef(New->isUndef());
lib/Target/AMDGPU/SIISelLowering.cpp 3234 SetOn->getOperand(3).setIsUndef();
3359 SetOn->getOperand(3).setIsUndef();
3370 SetOn->getOperand(3).setIsUndef();
3792 Br->getOperand(1).setIsUndef(true); // read undef SCC
lib/Target/AMDGPU/SIInstrInfo.cpp 2041 CondReg.setIsUndef(OrigCond.isUndef());
2094 CondReg.setIsUndef(Cond[1].isUndef());
3051 Use.setIsUndef(Orig.isUndef());
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 279 To.setIsUndef(From.isUndef());
lib/Target/AMDGPU/SIShrinkInstructions.cpp 297 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef);
lib/Target/ARM/ARMBaseInstrInfo.cpp 1633 MI.getOperand(1).setIsUndef();
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 942 MO.setIsUndef();
lib/Target/Hexagon/HexagonOptAddrMode.cpp 422 BaseOp.setIsUndef(AddRegOp.isUndef());
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 256 MI.getOperand(1).setIsUndef(KilledProdRegUndef);
257 MI.getOperand(3).setIsUndef(AddRegUndef);
267 MI.getOperand(2).setIsUndef(AddRegUndef);
272 MI.getOperand(2).setIsUndef(OtherProdRegUndef);
lib/Target/X86/X86ISelLowering.cpp31225 Push->getOperand(2).setIsUndef();
31228 Push->getOperand(3).setIsUndef();
unittests/MI/LiveIntervalTest.cpp 376 MI.getOperand(0).setIsUndef(false);
439 UndefSubregDef.getOperand(0).setIsUndef(false);
460 UndefSubregDef.getOperand(0).setIsUndef(false);