|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineInstrBuilder.h 55 ImplicitKill = Implicit | Kill
95 flags & RegState::Kill,
477 return B ? RegState::Kill : 0;
lib/CodeGen/MIRParser/MIParser.cpp 1302 Flags |= RegState::Kill;
1471 Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
lib/CodeGen/MachineBasicBlock.cpp 518 .addReg(PhysReg, RegState::Kill);
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1248 .addReg(EHPhysReg, RegState::Kill);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 212 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
299 .addUse(StatusReg, RegState::Kill)
300 .addUse(StatusReg, RegState::Kill)
510 .addReg(DstReg, RegState::Kill)
516 .addUse(DstReg, RegState::Kill);
lib/Target/AArch64/AArch64FastISel.cpp 502 .addReg(ResultReg, RegState::Kill)
lib/Target/AArch64/AArch64FrameLowering.cpp 1082 .addReg(AArch64::X16, RegState::Kill)
1097 .addReg(AArch64::SP, RegState::Kill)
1098 .addReg(AArch64::X15, RegState::Kill)
1150 .addReg(scratchSPReg, RegState::Kill)
lib/Target/AArch64/AArch64InstrInfo.cpp 1515 .addUse(Reg, RegState::Kill)
1521 .addReg(Reg, RegState::Kill)
1531 .addReg(Reg, RegState::Kill)
1535 .addReg(Reg, RegState::Kill)
1539 .addReg(Reg, RegState::Kill)
1543 .addReg(Reg, RegState::Kill)
1557 .addUse(Reg, RegState::Kill)
1563 .addReg(Reg, RegState::Kill)
lib/Target/AArch64/AArch64SpeculationHardening.cpp 400 .addUse(TmpReg, RegState::Kill | RegState::Renamable)
401 .addUse(MisspeculatingTaintReg, RegState::Kill)
406 .addUse(TmpReg, RegState::Kill)
578 .addUse(SrcReg, RegState::Kill)
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 375 .addReg(CarryReg, RegState::Kill)
967 .addReg(OverflowVal, RegState::Kill)
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 924 .addReg(CondReg, RegState::Kill);
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 899 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill);
lib/Target/AMDGPU/R600ISelLowering.cpp 408 .addReg(R600::PREDICATE_BIT, RegState::Kill);
422 .addReg(R600::PREDICATE_BIT, RegState::Kill);
lib/Target/AMDGPU/R600InstrInfo.cpp 777 .addReg(R600::PREDICATE_BIT, RegState::Kill);
792 .addReg(R600::PREDICATE_BIT, RegState::Kill);
1140 RegState::Implicit | RegState::Kill);
1173 RegState::Implicit | RegState::Kill);
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 311 .addReg(TmpReg, RegState::Kill);
lib/Target/AMDGPU/SIFoldOperands.cpp 264 .addReg(AMDGPU::VCC, RegState::Kill);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 144 S |= RegState::Kill;
385 B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg);
lib/Target/AMDGPU/SIFrameLowering.cpp 107 .addReg(SpillReg, RegState::Kill)
127 .addReg(SpillReg, RegState::Kill)
128 .addReg(OffsetReg, RegState::Kill)
175 .addReg(OffsetReg, RegState::Kill)
255 .addReg(FlatScrInitHi, RegState::Kill);
265 .addReg(FlatScrInitLo, RegState::Kill)
490 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
502 .addReg(PreloadedScratchWaveOffsetReg, HasFP ? RegState::Kill : 0);
507 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
753 .addReg(ScratchExecCopy, RegState::Kill);
798 .addReg(ScratchSPReg, RegState::Kill)
911 .addReg(ScratchExecCopy, RegState::Kill);
lib/Target/AMDGPU/SIISelLowering.cpp 3151 .addReg(Reg, RegState::Kill)
3214 .addReg(CondReg, RegState::Kill);
3225 .addReg(CurrentIdxReg, RegState::Kill)
3232 .addReg(IdxReg, RegState::Kill)
3239 .addReg(CurrentIdxReg, RegState::Kill);
3242 .addReg(CurrentIdxReg, RegState::Kill)
3367 .addReg(Tmp, RegState::Kill)
3713 .addReg(CountReg, RegState::Kill)
lib/Target/AMDGPU/SIInstrInfo.cpp 672 .addReg(Tmp, RegState::Kill);
4388 .addReg(AndCond, RegState::Kill);
4722 .addReg(CondReg0, RegState::Kill)
5392 .addReg(CarryReg, RegState::Kill)
5672 .addReg(ImmReg, RegState::Kill)
5678 .addReg(TmpReg, RegState::Kill);
5686 .addReg(ImmReg, RegState::Kill)
5701 .addReg(ImmReg, RegState::Kill)
5702 .addReg(TmpReg, RegState::Kill);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 916 BaseRegFlags = RegState::Kill;
943 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1009 BaseRegFlags = RegState::Kill;
1082 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1132 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1194 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1320 .addReg(SrcReg, RegState::Kill);
1410 .addReg(CarryReg, RegState::Kill)
lib/Target/AMDGPU/SILowerControlFlow.cpp 245 .addReg(Tmp, RegState::Kill);
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1198 Copy.addReg(Op.getReg(), Op.isKill() ? RegState::Kill : 0,
lib/Target/AMDGPU/SIRegisterInfo.cpp 372 .addReg(OffsetReg, RegState::Kill)
730 .addReg(TmpReg, RegState::Kill);
844 .addReg(TmpVGPR, RegState::Kill) // src
855 .addReg(M0CopyReg, RegState::Kill);
936 .addReg(TmpVGPR, RegState::Kill);
945 .addReg(M0CopyReg, RegState::Kill);
1128 .addReg(DiffReg, RegState::Kill);
1136 MIB.addReg(ScaledReg, RegState::Kill);
1148 MIB.addReg(ConstOffsetReg, RegState::Kill);
1149 MIB.addReg(ScaledReg, RegState::Kill);
1165 .addReg(DiffReg, RegState::Kill)
1168 .addReg(ScaledReg, RegState::Kill)
1171 .addReg(ScaledReg, RegState::Kill);
1176 .addReg(ScaledReg, RegState::Kill)
1179 .addReg(DiffReg, RegState::Kill)
lib/Target/ARC/ARCFrameLowering.cpp 167 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
297 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
465 .addReg(Reg, RegState::Kill)
lib/Target/ARC/ARCRegisterInfo.cpp 80 KillState = RegState::Kill;
lib/Target/ARM/ARMBaseInstrInfo.cpp 1561 STM.addReg(Reg, RegState::Kill);
2366 .addReg(BaseReg, RegState::Kill)
2389 .addReg(BaseReg, RegState::Kill)
4785 MIB.addReg(Reg, RegState::Kill).addImm(0);
4795 MIB.addReg(Reg, RegState::Kill)
lib/Target/ARM/ARMExpandPseudoInsts.cpp 956 .addReg(DesiredReg, RegState::Kill);
983 .addReg(ARM::CPSR, RegState::Kill);
1000 .addReg(TempReg, RegState::Kill)
1006 .addReg(ARM::CPSR, RegState::Kill);
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1104 .addReg(ARM::CPSR, RegState::Kill);
1120 .addReg(TempReg, RegState::Kill)
1126 .addReg(ARM::CPSR, RegState::Kill);
1201 .addReg(JumpTarget.getReg(), RegState::Kill);
1370 .addReg(ARM::R6, RegState::Kill)
1431 MIB.addReg(Reg, RegState::Kill);
1638 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1639 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
lib/Target/ARM/ARMFastISel.cpp 312 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
315 .addReg(Op0, Op0IsKill * RegState::Kill));
338 .addReg(Op0, Op0IsKill * RegState::Kill)
339 .addReg(Op1, Op1IsKill * RegState::Kill));
342 .addReg(Op0, Op0IsKill * RegState::Kill)
343 .addReg(Op1, Op1IsKill * RegState::Kill));
364 .addReg(Op0, Op0IsKill * RegState::Kill)
368 .addReg(Op0, Op0IsKill * RegState::Kill)
2726 MIB.addReg(SrcReg, isKill * RegState::Kill)
lib/Target/ARM/ARMFrameLowering.cpp 304 .addReg(Reg, RegState::Kill)
309 .addReg(Reg, RegState::Kill)
319 .addReg(Reg, RegState::Kill)
324 .addReg(Reg, RegState::Kill)
334 .addReg(Reg, RegState::Kill)
550 .addReg(ARM::R12, RegState::Kill)
557 .addReg(ARM::SP, RegState::Kill)
558 .addReg(ARM::R4, RegState::Kill)
734 .addReg(ARM::SP, RegState::Kill)
739 .addReg(ARM::R4, RegState::Kill)
1245 .addReg(ARM::R4, RegState::Kill)
1377 .addReg(ARM::R4, RegState::Kill)
lib/Target/ARM/ARMISelLowering.cpp 9386 .addReg(NewVReg1, RegState::Kill)
9392 .addReg(NewVReg2, RegState::Kill)
9395 .addReg(NewVReg3, RegState::Kill)
9415 .addReg(NewVReg1, RegState::Kill)
9426 .addReg(NewVReg2, RegState::Kill)
9427 .addReg(NewVReg3, RegState::Kill)
9434 .addReg(NewVReg4, RegState::Kill)
9435 .addReg(NewVReg5, RegState::Kill)
9452 .addReg(NewVReg1, RegState::Kill)
9456 .addReg(NewVReg2, RegState::Kill)
9617 .addReg(NewVReg3, RegState::Kill)
9624 .addReg(NewVReg4, RegState::Kill)
9682 .addReg(NewVReg2, RegState::Kill)
9691 .addReg(NewVReg4, RegState::Kill)
9701 .addReg(NewVReg5, RegState::Kill)
9707 .addReg(NewVReg6, RegState::Kill)
9760 .addReg(VReg1, RegState::Kill)
9784 .addReg(NewVReg3, RegState::Kill)
9792 .addReg(NewVReg5, RegState::Kill)
9797 .addReg(NewVReg5, RegState::Kill)
10292 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10307 .addReg(Reg, RegState::Kill)
10308 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10319 .addReg(ARM::SP, RegState::Kill)
10320 .addReg(ARM::R4, RegState::Kill)
10659 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
lib/Target/ARM/ARMInstrInfo.cpp 132 .addReg(Reg, RegState::Kill)
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 1548 MIB.addReg(BaseOp.getReg(), RegState::Kill)
1985 .addReg(Use.getReg(), RegState::Kill)
lib/Target/ARM/Thumb1FrameLowering.cpp 91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill)
413 .addReg(ARM::SP, RegState::Kill)
418 .addReg(ARM::R4, RegState::Kill)
424 .addReg(ARM::R4, RegState::Kill)
429 .addReg(ARM::R4, RegState::Kill)
729 .addReg(PopReg, RegState::Kill)
745 .addReg(PopReg, RegState::Kill)
782 .addReg(PopReg, RegState::Kill)
788 .addReg(TemporaryReg, RegState::Kill)
921 PushMIB.addReg(Reg, RegState::Kill);
1012 .addReg(*CopyReg, RegState::Kill)
lib/Target/ARM/Thumb2InstrInfo.cpp 239 .addReg(BaseReg, RegState::Kill)
272 .addReg(DestReg, RegState::Kill)
284 .addReg(DestReg, RegState::Kill)
354 .addReg(BaseReg, RegState::Kill)
lib/Target/ARM/ThumbRegisterInfo.cpp 160 .addReg(LdReg, RegState::Kill)
176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
315 MIB.addReg(BaseReg, RegState::Kill);
lib/Target/AVR/AVRExpandPseudoInsts.cpp 643 .addReg(SrcReg, RegState::Kill);
648 .addReg(SrcReg, RegState::Kill);
674 .addReg(SrcReg, RegState::Kill);
679 .addReg(SrcReg, RegState::Kill);
1057 .addReg(DstReg, RegState::Kill)
1063 .addReg(DstReg, RegState::Kill)
1091 .addReg(DstReg, RegState::Kill)
1097 .addReg(DstReg, RegState::Kill)
1394 .addReg(DstHiReg, RegState::Kill);
1398 .addReg(DstHiReg, RegState::Kill)
1399 .addReg(DstHiReg, RegState::Kill);
1437 .addReg(DstHiReg, RegState::Kill)
1438 .addReg(DstHiReg, RegState::Kill);
1497 .addReg(AVR::R0, RegState::Kill)
lib/Target/AVR/AVRFrameLowering.cpp 72 .addReg(AVR::R29R28, RegState::Kill)
81 .addReg(AVR::R1R0, RegState::Kill)
88 .addReg(AVR::R0, RegState::Kill)
92 .addReg(AVR::R0, RegState::Kill)
93 .addReg(AVR::R0, RegState::Kill)
132 .addReg(AVR::R29R28, RegState::Kill)
173 .addReg(AVR::R0, RegState::Kill);
209 .addReg(AVR::R29R28, RegState::Kill)
216 .addReg(AVR::R29R28, RegState::Kill);
404 .addReg(AVR::R31R30, RegState::Kill)
409 .addReg(AVR::R31R30, RegState::Kill);
527 .addReg(SPCopy, RegState::Kill);
lib/Target/AVR/AVRRegisterInfo.cpp 197 .addReg(DstReg, RegState::Kill)
225 .addReg(AVR::R29R28, RegState::Kill)
232 .addReg(AVR::R0, RegState::Kill);
237 .addReg(AVR::R29R28, RegState::Kill)
lib/Target/BPF/BPFInstrInfo.cpp 82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg)
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 638 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
644 SrcState &= ~RegState::Kill;
lib/Target/Hexagon/HexagonFrameLowering.cpp 1582 .addReg(TmpR, RegState::Kill);
1614 .addReg(TmpR, RegState::Kill)
1646 .addReg(TmpR, RegState::Kill);
1678 .addReg(TmpR0, RegState::Kill);
1716 .addReg(TmpR1, RegState::Kill)
1717 .addReg(TmpR0, RegState::Kill);
lib/Target/Hexagon/HexagonInstrInfo.cpp 1264 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1298 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
lib/Target/Hexagon/HexagonSplitDouble.cpp 653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
771 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
811 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
836 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
839 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
848 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
859 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
870 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
882 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
885 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
888 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
946 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
947 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
953 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
954 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
958 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
975 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
986 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
lib/Target/Hexagon/HexagonStoreWidening.cpp 460 .addReg(VReg, RegState::Kill);
lib/Target/MSP430/MSP430FrameLowering.cpp 67 .addReg(MSP430::FP, RegState::Kill);
200 .addReg(Reg, RegState::Kill);
lib/Target/Mips/Mips16InstrInfo.cpp 294 MIB2.addReg(Mips::SP, RegState::Kill);
297 MIB3.addReg(Reg2, RegState::Kill);
300 MIB4.addReg(Reg1, RegState::Kill);
421 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
426 .addReg(Reg, RegState::Kill);
lib/Target/Mips/MipsExpandPseudo.cpp 158 .addReg(Scratch, RegState::Kill)
161 .addReg(Scratch, RegState::Kill)
164 .addReg(Scratch, RegState::Kill)
168 .addReg(Scratch, RegState::Kill)
184 .addReg(Dest, RegState::Kill)
187 .addReg(Dest, RegState::Kill)
280 .addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB);
290 .addReg(Scratch, RegState::Kill).addReg(ZERO).addMBB(loop1MBB);
464 .addReg(Dest, RegState::Kill)
467 .addReg(Dest, RegState::Kill)
lib/Target/Mips/MipsISelLowering.cpp 1766 .addReg(PtrCopy, RegState::Kill)
1767 .addReg(OldValCopy, RegState::Kill)
1768 .addReg(NewValCopy, RegState::Kill)
lib/Target/Mips/MipsSEFrameLowering.cpp 179 .addReg(VR, RegState::Kill);
216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
274 .addReg(VR0, RegState::Kill);
277 .addReg(VR1, RegState::Kill);
lib/Target/Mips/MipsSEInstrInfo.cpp 602 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
641 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
769 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
lib/Target/Mips/MipsSERegisterInfo.cpp 248 .addReg(Reg, RegState::Kill);
lib/Target/PowerPC/PPCFrameLowering.cpp 391 .addReg(SrcReg, RegState::Kill)
400 .addReg(SrcReg, RegState::Kill)
409 .addReg(SrcReg, RegState::Kill)
413 .addReg(DstReg, RegState::Kill)
975 CrState = RegState::Kill;
1000 CrState = RegState::Kill;
1074 .addReg(ScratchReg, RegState::Kill)
1081 .addReg(TempReg, RegState::Kill)
1084 .addReg(ScratchReg, RegState::Kill)
1085 .addReg(TempReg, RegState::Kill);
1089 .addReg(SPReg, RegState::Kill)
1104 .addReg(ScratchReg, RegState::Kill)
1107 .addReg(SPReg, RegState::Kill)
1137 .addReg(ScratchReg, RegState::Kill)
1153 .addReg(FPReg, RegState::Kill) // Save FP.
1164 .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
1175 .addReg(BPReg, RegState::Kill) // Save BP.
1180 .addReg(ScratchReg, RegState::Kill)
1205 .addReg(ScratchReg, RegState::Kill)
1554 .addReg(ScratchReg, RegState::Kill)
1711 .addReg(ScratchReg, RegState::Kill)
2328 .addReg(StackReg, RegState::Kill)
2335 .addReg(TmpReg, RegState::Kill)
2338 .addReg(StackReg, RegState::Kill)
lib/Target/PowerPC/PPCInstrInfo.cpp 940 .addReg(DestReg, RegState::Kill)
1915 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
lib/Target/PowerPC/PPCRegisterInfo.cpp 569 .addReg(NegSizeReg1, RegState::Kill);
574 .addReg(Reg, RegState::Kill)
594 .addReg(NegSizeReg1, RegState::Kill);
599 .addReg(Reg, RegState::Kill)
673 .addReg(Reg1, RegState::Kill)
680 .addReg(Reg, RegState::Kill),
719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
724 .addReg(Reg, RegState::Kill);
798 .addReg(Reg1, RegState::Kill)
803 .addReg(Reg, RegState::Kill),
842 .addReg(RegO, RegState::Kill)
843 .addReg(Reg, RegState::Kill)
850 .addReg(RegO, RegState::Kill)
879 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
907 .addReg(Reg, RegState::Kill);
1107 .addReg(SRegHi, RegState::Kill)
lib/Target/RISCV/RISCVFrameLowering.cpp 90 .addReg(ScratchReg, RegState::Kill)
lib/Target/RISCV/RISCVInstrInfo.cpp 191 .addReg(SrcReg, RegState::Kill)
402 .addReg(ScratchReg, RegState::Kill)
lib/Target/RISCV/RISCVRegisterInfo.cpp 135 .addReg(ScratchReg, RegState::Kill);
lib/Target/SystemZ/SystemZFrameLowering.cpp 413 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
lib/Target/SystemZ/SystemZRegisterInfo.cpp 324 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 84 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
lib/Target/X86/X86FastISel.cpp 1839 .addReg(CReg, RegState::Kill);
2640 .addReg(InputReg, RegState::Kill);
2662 .addReg(InputReg, RegState::Kill);
lib/Target/X86/X86FrameLowering.cpp 293 .addReg(Rax, RegState::Kill)
1111 .addReg(MachineFramePtr, RegState::Kill)
1252 .addReg(X86::RAX, RegState::Kill)
1257 .addReg(X86::EAX, RegState::Kill)
2436 .addReg(ScratchReg2, RegState::Kill);
lib/Target/X86/X86ISelLowering.cpp30406 .addReg(AvailableReg, RegState::Implicit | RegState::Kill);
31271 .addReg(OldCW, RegState::Kill).addImm(0xC00);
31277 .addReg(NewCW, RegState::Kill, X86::sub_16bit);
31283 .addReg(NewCW16, RegState::Kill);
lib/Target/X86/X86InstrInfo.cpp 811 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
866 .addReg(OutRegLEA, RegState::Kill, SubReg);
4001 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5588 MIB.addReg(Reg, RegState::Kill);
7802 .addReg(PBReg, RegState::Kill)
7803 .addReg(GOTReg, RegState::Kill);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1149 .addReg(TargetReg, RegState::Kill)
1168 .addReg(TargetReg, RegState::Kill)
1169 .addReg(AddrReg, RegState::Kill);
1913 .addReg(PredStateReg, RegState::Kill)
1919 .addReg(TmpReg, RegState::Kill);
1938 .addReg(TmpReg, RegState::Kill)
2540 .addReg(ExpectedRetAddrReg, RegState::Kill)
2551 .addReg(ExpectedRetAddrReg, RegState::Kill)
2552 .addReg(ActualRetAddrReg, RegState::Kill);
2562 .addReg(NewStateReg, RegState::Kill)
lib/Target/XCore/XCoreFrameLowering.cpp 290 .addReg(SpillList[i].Reg, RegState::Kill)
lib/Target/XCore/XCoreRegisterInfo.cpp 108 .addReg(ScratchOffset, RegState::Kill)
115 .addReg(ScratchOffset, RegState::Kill)
121 .addReg(ScratchOffset, RegState::Kill);
184 .addReg(ScratchBase, RegState::Kill)
185 .addReg(ScratchOffset, RegState::Kill)
191 .addReg(ScratchBase, RegState::Kill)
192 .addReg(ScratchOffset, RegState::Kill)
197 .addReg(ScratchBase, RegState::Kill)
198 .addReg(ScratchOffset, RegState::Kill);