reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/LiveInterval.cpp

  930     LaneBitmask SRMask = SR.LaneMask;
  942       SR.LaneMask = SRMask & ~Matching;
  948       stripValuesNotDefiningMask(reg, SR, SR.LaneMask, Indexes, TRI);
 1032   OS << " L" << PrintLaneMask(LaneMask) << ' '
 1085     assert((Mask & SR.LaneMask).none());
 1086     Mask |= SR.LaneMask;
 1405               = LIV[ComponentNum-1]->createSubRange(Allocator, SR.LaneMask);

lib/CodeGen/LiveIntervals.cpp

  373       if ((SR.LaneMask & M).any()) {
  374         assert(SR.LaneMask == M && "Expecting lane masks to match exactly");
  559       if ((LaneMask & SR.LaneMask).none())
  587   extendSegmentsToUses(NewLR, WorkList, Reg, SR.LaneMask);
  772             DefinedLanesMask |= SR.LaneMask;
  999             if ((S.LaneMask & LaneMask).none())
 1001             updateRange(S, Reg, S.LaneMask);
 1620       repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);

lib/CodeGen/LiveRangeCalc.cpp

  121       SubLRC.extendToUses(S, Reg, S.LaneMask, &LI);

lib/CodeGen/LiveRangeEdit.cpp

   49       LI.createSubRange(Alloc, S.LaneMask);
  253     if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())

lib/CodeGen/LiveRegMatrix.cpp

   87         if ((S.LaneMask & Mask).any()) {

lib/CodeGen/MachineVerifier.cpp

 1981               if ((MOMask & SR.LaneMask).none())
 1983               checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
 1986                 LiveInMask |= SR.LaneMask;
 2083               if ((SR.LaneMask & MOMask).none())
 2085               checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
 2688     if ((Mask & SR.LaneMask).any()) {
 2692     if ((SR.LaneMask & ~MaxMask).any()) {
 2698       report_context(SR, LI.reg, SR.LaneMask);
 2700     Mask |= SR.LaneMask;
 2701     verifyLiveRange(SR, LI.reg, SR.LaneMask);

lib/CodeGen/RegisterCoalescer.cpp

  938       MaskA |= SA.LaneMask;
  941           Allocator, SA.LaneMask,
  958       if ((SB.LaneMask & MaskA).any())
 1357       SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
 1357       SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
 1392         MaxMask &= ~SR.LaneMask;
 1414         if ((SR.LaneMask & DstMask).none()) {
 1417                      << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n");
 1536       if ((SR.LaneMask & SrcMask).none())
 1575       if ((SR.LaneMask & DstMask).none())
 1597         if ((SR.LaneMask & UseMask).none())
 1632     if ((S.LaneMask & Mask).none())
 1936       if ((S.LaneMask & ShrinkMask).none())
 1938       LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask)
 2430         LaneBitmask SMask = TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
 3047         LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
 3067                           << PrintLaneMask(S.LaneMask) << " at " << Def
 3069         ShrinkMask |= S.LaneMask;
 3285           joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);
 3342         LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
 3343         R.LaneMask = Mask;
 3358         LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
 3736             assert((S.LaneMask & ~MaxMask).none());

lib/CodeGen/RegisterPressure.cpp

  431             Result |= SR.LaneMask;

lib/CodeGen/RenameIndependentSubregs.cpp

  186       if ((SR.LaneMask & LaneMask).none())
  231       if ((SR.LaneMask & LaneMask).none())
  284         SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask);

lib/CodeGen/SplitKit.cpp

  410     if (S.LaneMask == LM)
  427       auto &PS = getSubRangeForMask(S.LaneMask, Edit->getParent());
  451       if ((S.LaneMask & LM).any())
  660         LaneMask |= S.LaneMask;
 1288       LiveInterval::SubRange &S = getSubRangeForMask(PS.LaneMask, LI);
 1296       LI.computeSubRangeUndefs(Undefs, PS.LaneMask, MRI, *LIS.getSlotIndexes());
 1297       extendPHIRange(B, SubLRC, S, PS.LaneMask, Undefs);
 1380       if ((S.LaneMask & LM).none())
 1392       LI.computeSubRangeUndefs(Undefs, S.LaneMask, MRI, *LIS.getSlotIndexes());

lib/CodeGen/VirtRegMap.cpp

  301         LaneMask |= SR->LaneMask;
  368     if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))

lib/Target/AMDGPU/GCNRegPressure.cpp

  265         LiveMask |= S.LaneMask;
  384           It.second &= ~S.LaneMask;

lib/Target/AMDGPU/GCNRegPressure.h

  234           LiveRegMap[SII.getInstructionFromIndex(SI)][Reg] |= S.LaneMask;

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1881         if ((S.LaneMask & SubLanes) == SubLanes) {

lib/Target/Hexagon/HexagonExpandCondsets.cpp

  355           KillAt(I->end, S.LaneMask);
  530       updateDeadsInRange(Reg, S.LaneMask, S);