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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 974 /* 1712*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
992 /* 1746*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1010 /* 1777*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1026 /* 1806*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1047 /* 1843*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1064 /* 1875*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1082 /* 1907*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1098 /* 1936*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1140 /* 2018*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1158 /* 2050*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1174 /* 2079*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1212 /* 2154*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1230 /* 2185*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1246 /* 2214*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1267 /* 2251*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1284 /* 2283*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1302 /* 2315*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1318 /* 2344*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1360 /* 2426*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1378 /* 2458*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1394 /* 2487*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1439 /* 2574*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1457 /* 2605*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1473 /* 2634*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1494 /* 2671*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1511 /* 2703*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1529 /* 2735*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1545 /* 2764*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1587 /* 2846*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1605 /* 2878*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1621 /* 2907*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1659 /* 2982*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1677 /* 3013*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1693 /* 3042*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1714 /* 3079*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1731 /* 3111*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1749 /* 3143*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1765 /* 3172*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1807 /* 3254*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1825 /* 3286*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
1841 /* 3315*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
2011 /* 3676*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
2023 /* 3698*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
2036 /* 3720*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
2046 /* 3738*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
2084 /* 3831*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
2097 /* 3853*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
2107 /* 3871*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
65548 /*159745*/ /*SwitchOpcode*/ 35, TARGET_VAL(ISD::ZERO_EXTEND),// ->159783
65591 /*159829*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::ZERO_EXTEND),// ->159866
65679 /*160005*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::ZERO_EXTEND),// ->160028
65683 /*160011*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
65711 /*160060*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::ZERO_EXTEND),// ->160084
65715 /*160066*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
66233 /*161036*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
66371 /*161286*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
66836 /*162125*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::ZERO_EXTEND),// ->162246
66846 /*162143*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
66867 /*162180*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
66888 /*162217*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
67113 /*162620*/ OPC_SwitchOpcode /*2 cases */, 93|128,1/*221*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->162846
67275 /*162920*/ OPC_SwitchOpcode /*2 cases */, 102|128,1/*230*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->163155
69235 /*166491*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::ZERO_EXTEND),// ->166569
69241 /*166501*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
69255 /*166525*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
69269 /*166549*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
69355 /*166715*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::ZERO_EXTEND),// ->166769
69523 /*167026*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ZERO_EXTEND),// ->167083
83330 /*193245*/ OPC_SwitchOpcode /*3 cases */, 41, TARGET_VAL(ISD::ZERO_EXTEND),// ->193290
86713 /*200208*/ /*SwitchOpcode*/ 62, TARGET_VAL(ISD::ZERO_EXTEND),// ->200273
86735 /*200252*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
86807 /*200395*/ /*SwitchOpcode*/ 56, TARGET_VAL(ISD::ZERO_EXTEND),// ->200454
86828 /*200436*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87263 /*201254*/ /*SwitchOpcode*/ 118, TARGET_VAL(ISD::ZERO_EXTEND),// ->201375
87273 /*201272*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87294 /*201309*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87315 /*201346*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87541 /*201757*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ZERO_EXTEND),// ->201827
87744 /*202137*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87750 /*202147*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87764 /*202171*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87778 /*202195*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
87918 /*202458*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::ZERO_EXTEND),// ->202512
88543 /*203797*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88554 /*203816*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88581 /*203861*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88607 /*203907*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88618 /*203926*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88639 /*203960*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88656 /*203991*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88667 /*204010*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88700 /*204065*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88732 /*204120*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88743 /*204139*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
88770 /*204184*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
91610 /*208919*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
91685 /*209066*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
91745 /*209186*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
91820 /*209333*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
92663 /*210930*/ /*SwitchOpcode*/ 60, TARGET_VAL(ISD::ZERO_EXTEND),// ->210993
92684 /*210973*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
94587 /*214760*/ OPC_SwitchOpcode /*3 cases */, 41, TARGET_VAL(ISD::ZERO_EXTEND),// ->214805
94916 /*215428*/ OPC_SwitchOpcode /*3 cases */, 41, TARGET_VAL(ISD::ZERO_EXTEND),// ->215473
95197 /*215952*/ OPC_SwitchOpcode /*3 cases */, 41, TARGET_VAL(ISD::ZERO_EXTEND),// ->215997
96315 /*218042*/ /*SwitchOpcode*/ 37|128,4/*549*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->218595
99531 /*224173*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
99542 /*224193*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
99563 /*224229*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
99584 /*224265*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
99606 /*224301*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
99620 /*224324*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
99634 /*224347*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
107778 /*240823*/ /*SwitchOpcode*/ 42|128,2/*298*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->241125
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc59806 /*130776*/ /*SwitchOpcode*/ 2|128,7/*898*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->131678
gen/lib/Target/ARM/ARMGenDAGISel.inc 5826 /* 11929*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
5929 /* 12138*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
7195 /* 14721*/ /*SwitchOpcode*/ 95, TARGET_VAL(ISD::ZERO_EXTEND),// ->14819
7201 /* 14731*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
7217 /* 14763*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
7232 /* 14793*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
8138 /* 16908*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::ZERO_EXTEND),// ->16984
8380 /* 17461*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::ZERO_EXTEND),// ->17540
30963 /* 68159*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
30967 /* 68165*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
30982 /* 68191*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
30986 /* 68198*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
30995 /* 68214*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
30999 /* 68221*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31020 /* 68263*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31024 /* 68270*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31033 /* 68285*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31037 /* 68292*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31057 /* 68334*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31061 /* 68340*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31070 /* 68355*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31074 /* 68362*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31090 /* 68389*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31094 /* 68396*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31114 /* 68437*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31118 /* 68443*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31127 /* 68457*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31131 /* 68464*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31145 /* 68488*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
31149 /* 68495*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
33851 /* 74472*/ /*SwitchOpcode*/ 95, TARGET_VAL(ISD::ZERO_EXTEND),// ->74570
33857 /* 74482*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
33873 /* 74514*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
33888 /* 74544*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
34071 /* 74958*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::ZERO_EXTEND),// ->75034
46844 /*103909*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
46850 /*103919*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
46867 /*103952*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
46969 /*104185*/ /*SwitchOpcode*/ 85|128,3/*469*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->104658
47166 /*104666*/ OPC_SwitchOpcode /*3 cases */, 60|128,1/*188*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->104859
gen/lib/Target/ARM/ARMGenFastISel.inc 2729 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AVR/AVRGenDAGISel.inc 1390 /* 2419*/ /*SwitchOpcode*/ 9, TARGET_VAL(ISD::ZERO_EXTEND),// ->2431
gen/lib/Target/BPF/BPFGenDAGISel.inc 1831 /* 3204*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::ZERO_EXTEND),// ->3237
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc20374 /* 38888*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
20684 /* 39467*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::ZERO_EXTEND),// ->39513
21711 /* 41397*/ OPC_SwitchOpcode /*2 cases */, 42|128,1/*170*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->41572
21722 /* 41418*/ OPC_SwitchOpcode /*2 cases */, 73, TARGET_VAL(ISD::ZERO_EXTEND),// ->41495
21770 /* 41519*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
21804 /* 41597*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
21816 /* 41617*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
21836 /* 41669*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::ZERO_EXTEND),// ->41745
21847 /* 41688*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
21872 /* 41747*/ /*SwitchOpcode*/ 51|128,1/*179*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->41930
21882 /* 41766*/ OPC_SwitchOpcode /*2 cases */, 78, TARGET_VAL(ISD::ZERO_EXTEND),// ->41848
21933 /* 41872*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
21975 /* 41966*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
21986 /* 41985*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22007 /* 42038*/ /*SwitchOpcode*/ 73, TARGET_VAL(ISD::ZERO_EXTEND),// ->42114
22017 /* 42056*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22042 /* 42115*/ /*SwitchOpcode*/ 46|128,1/*174*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->42293
22055 /* 42139*/ OPC_SwitchOpcode /*2 cases */, 73, TARGET_VAL(ISD::ZERO_EXTEND),// ->42216
22102 /* 42239*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22125 /* 42294*/ /*SwitchOpcode*/ 55|128,1/*183*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->42481
22137 /* 42317*/ OPC_SwitchOpcode /*2 cases */, 78, TARGET_VAL(ISD::ZERO_EXTEND),// ->42399
22187 /* 42422*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22220 /* 42500*/ OPC_SwitchOpcode /*2 cases */, 76|128,1/*204*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->42709
22231 /* 42521*/ OPC_SwitchOpcode /*2 cases */, 90, TARGET_VAL(ISD::ZERO_EXTEND),// ->42615
22289 /* 42639*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22333 /* 42734*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22345 /* 42754*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22375 /* 42823*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::ZERO_EXTEND),// ->42916
22386 /* 42842*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22421 /* 42918*/ /*SwitchOpcode*/ 85|128,1/*213*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->43135
22431 /* 42937*/ OPC_SwitchOpcode /*2 cases */, 95, TARGET_VAL(ISD::ZERO_EXTEND),// ->43036
22492 /* 43060*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22544 /* 43171*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22555 /* 43190*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22586 /* 43260*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::ZERO_EXTEND),// ->43353
22596 /* 43278*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22631 /* 43354*/ /*SwitchOpcode*/ 80|128,1/*208*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->43566
22644 /* 43378*/ OPC_SwitchOpcode /*2 cases */, 90, TARGET_VAL(ISD::ZERO_EXTEND),// ->43472
22701 /* 43495*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
22734 /* 43567*/ /*SwitchOpcode*/ 89|128,1/*217*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->43788
22746 /* 43590*/ OPC_SwitchOpcode /*2 cases */, 95, TARGET_VAL(ISD::ZERO_EXTEND),// ->43689
22806 /* 43712*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
25459 /* 48900*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::ZERO_EXTEND),// ->48929
25464 /* 48908*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
25509 /* 48988*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::ZERO_EXTEND),// ->49018
25514 /* 48996*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
26341 /* 50599*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::ZERO_EXTEND),// ->50628
26346 /* 50607*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
52265 /* 98565*/ /*SwitchOpcode*/ 72|128,6/*840*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->99409
64620 /*124129*/ OPC_SwitchOpcode /*2 cases */, 22, TARGET_VAL(ISD::ZERO_EXTEND),// ->124155
64625 /*124138*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 4465 /* 8929*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::ZERO_EXTEND),// ->8980
gen/lib/Target/Mips/MipsGenDAGISel.inc14947 /* 27580*/ /*SwitchOpcode*/ 45|128,1/*173*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->27757
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc53073 /*114561*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::ZERO_EXTEND),// ->114625
53238 /*114859*/ /*SwitchOpcode*/ 103, TARGET_VAL(ISD::ZERO_EXTEND),// ->114965
53258 /*114894*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
53287 /*114944*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
68532 /*144909*/ /*SwitchOpcode*/ 54|128,1/*182*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->145095
gen/lib/Target/PowerPC/PPCGenDAGISel.inc 7038 /* 16890*/ /*SwitchOpcode*/ 49|128,76/*9777*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->26671
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2966 /* 5474*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::ZERO_EXTEND),// ->5495
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 5024 /* 9875*/ OPC_SwitchOpcode /*2 cases */, 13, TARGET_VAL(ISD::ZERO_EXTEND),// ->9892
7439 /* 14377*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::ZERO_EXTEND),// ->14423
14194 /* 26132*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::ZERO_EXTEND),// ->26152
16880 /* 31227*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
16900 /* 31264*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::ZERO_EXTEND),// ->31281
17190 /* 31835*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
17598 /* 32655*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
21395 /* 40199*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::ZERO_EXTEND),// ->40212
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 4763 /* 8622*/ /*SwitchOpcode*/ 9|128,17/*2185*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->10811
17983 /* 34526*/ OPC_SwitchOpcode /*2 cases */, 24, TARGET_VAL(ISD::ZERO_EXTEND),// ->34554
17987 /* 34533*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
18123 /* 34773*/ OPC_SwitchOpcode /*2 cases */, 24, TARGET_VAL(ISD::ZERO_EXTEND),// ->34801
18127 /* 34780*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
18263 /* 35020*/ OPC_SwitchOpcode /*2 cases */, 24, TARGET_VAL(ISD::ZERO_EXTEND),// ->35048
18267 /* 35027*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 981 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc55377 /*117371*/ /*SwitchOpcode*/ 86|128,5/*726*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->118101
125258 /*257716*/ /*SwitchOpcode*/ 55, TARGET_VAL(ISD::ZERO_EXTEND),// ->257774
127591 /*262285*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ZERO_EXTEND),// ->262342
146178 /*298900*/ OPC_CheckOpcode, TARGET_VAL(ISD::ZERO_EXTEND),
148005 /*302431*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::ZERO_EXTEND),// ->302488
160150 /*325310*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::ZERO_EXTEND),// ->325332
161810 /*328536*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::ZERO_EXTEND),// ->328557
187512 /*378916*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::ZERO_EXTEND),// ->378938
188253 /*380363*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::ZERO_EXTEND),// ->380384
gen/lib/Target/X86/X86GenFastISel.inc 5927 case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
include/llvm/CodeGen/TargetLowering.h 218 return ISD::ZERO_EXTEND;
1882 return ISD::ZERO_EXTEND;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1127 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1552 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1659 case ISD::ZERO_EXTEND:
2005 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2140 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2143 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
2363 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2467 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
3088 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
4040 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
4041 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
4159 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
4160 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
4270 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4648 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
4812 case ISD::ZERO_EXTEND:
5108 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
5269 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
5274 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
6255 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
6259 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
6373 case ISD::ZERO_EXTEND: {
6381 return Op.getOpcode() == ISD::ZERO_EXTEND
6445 case ISD::ZERO_EXTEND:
6923 if (isOneConstant(N1) && N0Opcode == ISD::ZERO_EXTEND && N0.hasOneUse() &&
6930 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, V);
7374 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
7418 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
7437 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
8240 NotCond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, NotCond);
8253 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
8273 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
8286 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
8654 auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
8757 auto ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
8893 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
8911 (Opcode != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0.getValueType(), VT))) {
8947 Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG;
8990 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
9061 N->getOpcode() == ISD::ZERO_EXTEND) &&
9157 assert(N->getOpcode() == ISD::ZERO_EXTEND);
9198 ISD::ZERO_EXTEND, SetCCs, TLI))
9216 ExtendSetCCUses(SetCCs, N1.getOperand(0), ExtLoad, ISD::ZERO_EXTEND);
9238 assert((CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND ||
9382 N->getOpcode() == ISD::ZERO_EXTEND) && "Expected sext or zext");
9614 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
9616 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0);
9625 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND &&
9634 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
9680 assert((Extend->getOpcode() == ISD::ZERO_EXTEND ||
9708 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
9709 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
9750 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
9792 ISD::ZEXTLOAD, ISD::ZERO_EXTEND))
9797 ISD::ZERO_EXTEND))
9831 ISD::ZERO_EXTEND, SetCCs, TLI);
9842 ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::ZERO_EXTEND);
9922 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
9939 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
9942 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
9966 N0.getOpcode() == ISD::ZERO_EXTEND ||
10422 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
10559 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
10809 N00.getOpcode() == ISD::ZERO_EXTEND ||
12865 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
12962 : ISD::ZERO_EXTEND;
13925 Val = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(LD), LDType, Val);
14348 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
14409 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
16451 if (Lo.getOpcode() != ISD::ZERO_EXTEND || !Lo.hasOneUse() ||
16454 Hi.getOpcode() != ISD::ZERO_EXTEND || !Hi.hasOneUse() ||
16477 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Lo.getOperand(0));
16478 Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Hi.getOperand(0));
17082 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
17133 Cast.getOpcode() == ISD::ZERO_EXTEND ||
17310 if (Zext.getOpcode() != ISD::ZERO_EXTEND || !Zext.hasOneUse() ||
17587 FoundZeroExtend |= (Opc == ISD::ZERO_EXTEND);
17588 if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND) &&
17620 return DAG.getNode(FoundZeroExtend ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, DL,
20119 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC);
20122 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), VT, SCC);
lib/CodeGen/SelectionDAG/FastISel.cpp 1886 return selectCast(I, ISD::ZERO_EXTEND);
1899 return selectCast(I, ISD::ZERO_EXTEND);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1539 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
2491 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2775 case ISD::ZERO_EXTEND:
3263 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3305 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3311 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3412 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
4144 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4169 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4247 ExtOp = ISD::ZERO_EXTEND;
4263 unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4324 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4337 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 810 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1557 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1565 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 114 case ISD::ZERO_EXTEND:
421 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
562 if (N->getOpcode() == ISD::ZERO_EXTEND)
953 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
1112 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1114 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1191 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1713 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
3405 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow),
3406 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RHSLow));
3535 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 970 Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 397 case ISD::ZERO_EXTEND:
580 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 103 case ISD::ZERO_EXTEND:
429 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
600 case ISD::ZERO_EXTEND:
925 case ISD::ZERO_EXTEND:
2023 case ISD::ZERO_EXTEND:
2842 case ISD::ZERO_EXTEND:
3288 if (Opcode == ISD::ZERO_EXTEND)
3416 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
4158 case ISD::ZERO_EXTEND:
4267 case ISD::ZERO_EXTEND:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 337 return ISD::ZERO_EXTEND;
1118 getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
2990 case ISD::ZERO_EXTEND: {
4298 case ISD::ZERO_EXTEND:
4438 case ISD::ZERO_EXTEND:
4509 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
4515 case ISD::ZERO_EXTEND:
4528 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
4529 return getNode(ISD::ZERO_EXTEND, DL, VT, Operand.getOperand(0));
4548 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
4579 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
5649 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, IntVT, Value);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 261 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
905 ExtendKind = ISD::ZERO_EXTEND;
1841 ExtendKind = ISD::ZERO_EXTEND;
1882 else if (ExtendKind == ISD::ZERO_EXTEND)
3147 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
3392 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
9206 ExtendKind = ISD::ZERO_EXTEND;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 313 case ISD::ZERO_EXTEND: return "zero_extend";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1620 case ISD::ZERO_EXTEND:
1695 IsVecInReg ? ISD::ZERO_EXTEND_VECTOR_INREG : ISD::ZERO_EXTEND;
1847 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Sign);
2538 case ISD::ZERO_EXTEND:
2543 if (Op.getOpcode() == ISD::ZERO_EXTEND) {
3152 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
3214 (N0Opc == ISD::ZERO_EXTEND || N0Opc == ISD::SIGN_EXTEND) &&
3294 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
4082 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue()
5708 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
5709 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
5714 SDValue Next = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Hi);
5755 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RL));
5759 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LL));
6421 SDValue ExtElt = DAG.getNode(ISD::ZERO_EXTEND, SL, IntVT, Trunc);
6756 MaskInIntReg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, MaskInIntReg);
6870 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
7206 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
lib/CodeGen/TargetLoweringBase.cpp 1479 ExtendKind = ISD::ZERO_EXTEND;
1618 case ZExt: return ISD::ZERO_EXTEND;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 469 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
2529 if (ShiftAmt->getOpcode() == ISD::ZERO_EXTEND ||
lib/Target/AArch64/AArch64ISelLowering.cpp 602 setTargetDAGCombine(ISD::ZERO_EXTEND);
2135 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2523 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2675 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2704 return N->getOpcode() == ISD::ZERO_EXTEND ||
3876 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3882 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
4195 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
4635 TLSIndex = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TLSIndex);
4907 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
4916 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
9694 ConvInput = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,
10236 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
10312 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
10533 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
10543 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
11746 case ISD::ZERO_EXTEND:
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 302 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
304 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
306 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
308 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
310 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
312 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
314 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
316 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1819 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
2386 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);
3032 case ISD::ZERO_EXTEND:
3409 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);
lib/Target/AMDGPU/SIISelLowering.cpp 567 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
572 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
723 setTargetDAGCombine(ISD::ZERO_EXTEND);
2326 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2796 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
4200 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4995 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
5003 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
6758 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, EquivStoreVT, IntVData);
7240 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, Op);
8508 if (LHS.getOpcode() == ISD::ZERO_EXTEND &&
8509 RHS.getOpcode() != ISD::ZERO_EXTEND)
8512 if (RHS.getOpcode() == ISD::ZERO_EXTEND) {
9039 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
9528 if (Opc == ISD::ZERO_EXTEND || Opc == ISD::SIGN_EXTEND ||
9535 case ISD::ZERO_EXTEND:
9873 if (Srl.getOpcode() == ISD::ZERO_EXTEND)
10001 case ISD::ZERO_EXTEND:
lib/Target/ARC/ARCISelLowering.cpp 276 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
lib/Target/ARM/ARMISelLowering.cpp 927 setTargetDAGCombine(ISD::ZERO_EXTEND);
2146 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2767 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
5415 CastOpc = ISD::ZERO_EXTEND;
5722 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
8278 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
8352 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
8364 unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
8617 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
8618 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
8645 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
8646 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
10856 case ISD::ZERO_EXTEND:
10872 else if (N->getOpcode() == ISD::ZERO_EXTEND)
10993 !(N0.getOpcode() == ISD::ZERO_EXTEND &&
10994 N1.getOpcode() == ISD::ZERO_EXTEND))
13569 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
13919 case ISD::ZERO_EXTEND:
14454 case ISD::ZERO_EXTEND:
lib/Target/ARM/ARMSelectionDAGInfo.cpp 93 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
lib/Target/ARM/ARMTargetTransformInfo.cpp 178 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0},
180 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0},
182 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0},
184 {ISD::ZERO_EXTEND, MVT::i64, MVT::i32, 1},
186 {ISD::ZERO_EXTEND, MVT::i64, MVT::i16, 1},
188 {ISD::ZERO_EXTEND, MVT::i64, MVT::i8, 1},
196 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0},
198 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0},
200 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0},
215 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
217 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
223 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
225 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
227 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
229 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
231 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
361 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
363 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
365 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 2 },
367 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
369 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
371 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 2 },
lib/Target/AVR/AVRISelLowering.cpp 1212 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg);
lib/Target/BPF/BPFISelLowering.cpp 340 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 1159 if (Opc != ISD::ZERO_EXTEND)
1500 case ISD::ZERO_EXTEND:
lib/Target/Hexagon/HexagonISelLowering.cpp 402 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 103 setOperationAction(ISD::ZERO_EXTEND, T, Custom);
136 setOperationAction(ISD::ZERO_EXTEND, T, Custom);
1208 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Op), ResTy, InpV);
1547 case ISD::ZERO_EXTEND:
1565 case ISD::ZERO_EXTEND: return LowerHvxZeroExt(Op, DAG);
lib/Target/Lanai/LanaiISelLowering.cpp 670 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1369 case ISD::ZERO_EXTEND: {
lib/Target/MSP430/MSP430ISelLowering.cpp 824 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
lib/Target/Mips/MipsISelLowering.cpp 1019 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1020 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
2269 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2290 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
3189 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3693 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
lib/Target/Mips/MipsSEISelLowering.cpp 1496 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
lib/Target/NVPTX/NVPTXISelLowering.cpp 1523 : ISD::ZERO_EXTEND,
2418 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2612 : ISD::ZERO_EXTEND;
2700 : ISD::ZERO_EXTEND,
4527 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4591 } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 1343 case ISD::ZERO_EXTEND: {
2506 case ISD::ZERO_EXTEND:
2531 assert((N->getOpcode() == ISD::ZERO_EXTEND ||
2539 N->getOpcode() == ISD::ZERO_EXTEND)
2763 Input.getOperand(0).getOpcode() == ISD::ZERO_EXTEND);
3564 CompareUse->getOpcode() != ISD::ZERO_EXTEND &&
3634 case ISD::ZERO_EXTEND:
4231 (TrueResVal == -1 && FalseRes.getOpcode() != ISD::ZERO_EXTEND) ||
5466 if (N->getOpcode() != ISD::ZERO_EXTEND &&
lib/Target/PowerPC/PPCISelLowering.cpp 1129 setTargetDAGCombine(ISD::ZERO_EXTEND);
5576 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5909 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
6472 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
6537 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
6843 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
6917 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
7148 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
7840 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
7866 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
8014 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
11947 auto Op0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(0),
11949 auto Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1),
11989 if (UI->getOpcode() != ISD::ZERO_EXTEND)
12084 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
12096 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
12106 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
12137 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
12149 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
12239 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
12442 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
12470 else if (N->getOpcode() == ISD::ZERO_EXTEND)
12534 else if (N->getOpcode() == ISD::ZERO_EXTEND)
12562 if (N->getOpcode() == ISD::ZERO_EXTEND)
13396 case ISD::ZERO_EXTEND:
15189 if (Op.getOpcode() != ISD::ZERO_EXTEND || !Op.hasOneUse() ||
15486 if ((SubOpcd0 == ISD::ZERO_EXTEND ||
15488 (SubOpcd1 == ISD::ZERO_EXTEND ||
lib/Target/Sparc/SparcISelLowering.cpp 328 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
346 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
809 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1151 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1202 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
2920 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2921 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 706 if (Index.getOpcode() == ISD::ZERO_EXTEND)
847 case ISD::ZERO_EXTEND:
1521 case ISD::ZERO_EXTEND:
lib/Target/SystemZ/SystemZISelLowering.cpp 607 setTargetDAGCombine(ISD::ZERO_EXTEND);
1275 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
2119 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
2917 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
3334 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
6158 case ISD::ZERO_EXTEND: return combineZERO_EXTEND(N, DCI);
lib/Target/X86/X86FastISel.cpp 1239 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
1568 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
3358 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg,
3370 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg,
lib/Target/X86/X86ISelDAGToDAG.cpp 860 ? ISD::ZERO_EXTEND
1759 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
2045 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
2133 case ISD::ZERO_EXTEND: {
2157 SDValue Zext = CurDAG->getNode(ISD::ZERO_EXTEND, DL, VT, Shl.getOperand(0));
3421 ShiftAmt = CurDAG->getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShiftAmt);
lib/Target/X86/X86ISelLowering.cpp 781 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
1142 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1143 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1161 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1325 setOperationAction(ISD::ZERO_EXTEND, VT, Custom);
1410 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1411 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1419 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i8, Custom);
1622 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1635 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1653 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1864 setTargetDAGCombine(ISD::ZERO_EXTEND);
2510 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
3774 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
4009 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
4216 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
4515 return (ISD::ZERO_EXTEND == Opcode);
5828 case ISD::ZERO_EXTEND:
5843 ISD::ZERO_EXTEND == Opcode) &&
7199 case ISD::ZERO_EXTEND:
8185 (Ld && Ld.getOpcode() == ISD::ZERO_EXTEND &&
9558 if (ExtractedIndex.getOpcode() == ISD::ZERO_EXTEND ||
9723 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
11987 InputV = getExtendInVec(AnyExt ? ISD::ANY_EXTEND : ISD::ZERO_EXTEND, DL,
12297 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
18817 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, N0);
19037 assert((Opc == ISD::ANY_EXTEND || Opc == ISD::ZERO_EXTEND) &&
19088 bool NeedZero = Opc == ISD::ZERO_EXTEND;
19132 return SplitAndExtendv16i1(ISD::ZERO_EXTEND, VT, In, DL, DAG);
20157 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
21638 : ISD::ZERO_EXTEND;
22544 else if (ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
23183 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
23205 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32,
23447 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
23509 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
24129 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
24583 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
24650 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
24778 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
25251 unsigned ExAVX = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
25625 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
25627 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
25642 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
25990 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
25992 Amt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Amt);
26737 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Lo);
26964 Op = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, Op0);
27696 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
27843 Wide = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Wide);
28045 case ISD::ZERO_EXTEND: {
28228 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, Src);
31857 Shuffle = unsigned(MatchAny ? ISD::ANY_EXTEND : ISD::ZERO_EXTEND);
35704 if (Op0.getOpcode() != ISD::ZERO_EXTEND ||
35706 Op1.getOpcode() != ISD::ZERO_EXTEND ||
35988 Root.getOpcode() == ISD::ZERO_EXTEND ||
36706 SDValue R = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
37390 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
37435 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
37518 Carry.getOpcode() == ISD::ZERO_EXTEND ||
37621 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
37635 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
37668 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
37899 return DAG.getNode((Mode == MULU8) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND,
38044 (N0.getOpcode() == ISD::ZERO_EXTEND &&
38046 (N1.getOpcode() == ISD::ZERO_EXTEND &&
38283 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
38685 case ISD::ZERO_EXTEND:
38789 N->getOpcode() == ISD::ZERO_EXTEND ||
38829 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N1);
38838 case ISD::ZERO_EXTEND:
39079 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Parity);
39101 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0), Setnp);
39191 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64,
39585 Ret = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), Ret);
39815 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, ResultType, Cond);
40139 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
40159 if (ISD::ZERO_EXTEND != V.getOpcode())
40188 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
40954 Opcode == ISD::ZERO_EXTEND) &&
41199 if ((ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND) ||
41253 if (N01.getOpcode() == ISD::ZERO_EXTEND)
41255 if (N11.getOpcode() == ISD::ZERO_EXTEND)
41259 if (N00.getOpcode() != ISD::ZERO_EXTEND ||
41261 N10.getOpcode() != ISD::ZERO_EXTEND ||
42146 CMovOp0 = DAG.getNode(ISD::ZERO_EXTEND, DL, CMovVT, CMovOp0);
42147 CMovOp1 = DAG.getNode(ISD::ZERO_EXTEND, DL, CMovVT, CMovOp1);
42204 Ext->getOpcode() != ISD::ZERO_EXTEND)
42325 if (Opcode != ISD::SIGN_EXTEND && Opcode != ISD::ZERO_EXTEND &&
42444 if (N->getOpcode() == ISD::ZERO_EXTEND)
42473 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
42727 if (X.getOpcode() == ISD::ZERO_EXTEND) {
43005 Index.getOpcode() == ISD::ZERO_EXTEND) &&
43194 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
43542 if (!IsSub && X.getOpcode() == ISD::ZERO_EXTEND &&
43543 Y.getOpcode() != ISD::ZERO_EXTEND)
43548 if (Y.getOpcode() == ISD::ZERO_EXTEND && Y.hasOneUse()) {
44098 if (Op0.getOpcode() == ISD::ZERO_EXTEND &&
44106 if (Op1.getOpcode() == ISD::ZERO_EXTEND &&
44725 InOpcode == ISD::ZERO_EXTEND ||
44956 case ISD::ZERO_EXTEND: return combineZext(N, DAG, DCI, Subtarget);
45066 case ISD::ZERO_EXTEND:
45141 case ISD::ZERO_EXTEND:
45606 SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, DL, OpInfo.ConstraintVT, CC);
45724 int64_t ExtVal = ExtOpc == ISD::ZERO_EXTEND ? CST->getZExtValue()
lib/Target/X86/X86TargetTransformInfo.cpp 1282 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 },
1293 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 },
1294 { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 },
1295 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 },
1296 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 },
1297 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 },
1298 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 },
1346 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
1348 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
1350 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
1352 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
1354 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
1356 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
1409 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 3 },
1411 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 3 },
1413 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 1 },
1415 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 1 },
1417 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 1 },
1419 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 },
1421 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
1423 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
1440 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 4 },
1442 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 4 },
1444 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1446 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 4 },
1448 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 4 },
1450 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1452 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 4 },
1454 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 4 },
1518 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 2 },
1520 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 2 },
1522 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 },
1525 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1527 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 1 },
1529 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1531 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 2 },
1533 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 2 },
1535 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 4 },
1537 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1539 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
1541 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
1585 { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
1587 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 2 },
1589 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8, 4 },
1591 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 1 },
1593 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 6 },
1595 { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i8, 3 },
1597 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 9 },
1599 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 1 },
1601 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
1603 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 3 },
1605 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
1607 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 3 },
lib/Target/XCore/XCoreISelLowering.cpp 1153 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);