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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc53389 /*119360*/ /*SwitchOpcode*/ 54|128,3/*438*/, TARGET_VAL(ISD::VSELECT),// ->119802
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68502 /*132668*/ /*SwitchOpcode*/ 126|128,16/*2174*/, TARGET_VAL(ISD::VSELECT),// ->134846
gen/lib/Target/Mips/MipsGenDAGISel.inc28200 /* 53297*/ /*SwitchOpcode*/ 64|128,2/*320*/, TARGET_VAL(ISD::VSELECT),// ->53621
gen/lib/Target/PowerPC/PPCGenDAGISel.inc42483 /*106629*/ /*SwitchOpcode*/ 81|128,2/*337*/, TARGET_VAL(ISD::VSELECT),// ->106970
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc26753 /* 50871*/ /*SwitchOpcode*/ 5|128,18/*2309*/, TARGET_VAL(ISD::VSELECT),// ->53184
gen/lib/Target/X86/X86GenDAGISel.inc75504 /*159265*/ /*SwitchOpcode*/ 57|128,76|128,13/*222777*/, TARGET_VAL(ISD::VSELECT),// ->382047
include/llvm/CodeGen/BasicTTIImpl.h 835 ISD = ISD::VSELECT;
include/llvm/CodeGen/SelectionDAG.h 996 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1547 case ISD::VSELECT: return visitVSELECT(N);
9247 if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
9251 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() ||
9274 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB);
20440 ISD::NodeType SelOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 76 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
806 return DAG.getNode(ISD::VSELECT, SDLoc(N),
1172 case ISD::VSELECT:
1414 if (N->getOpcode() == ISD::VSELECT)
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 394 case ISD::VSELECT:
782 case ISD::VSELECT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 60 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
619 case ISD::VSELECT:
845 case ISD::VSELECT:
2003 case ISD::VSELECT:
2100 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
2102 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
2717 case ISD::VSELECT:
3902 if (N->getOpcode() != ISD::VSELECT)
4001 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
4153 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2752 case ISD::VSELECT:
3591 case ISD::VSELECT:
5500 case ISD::VSELECT:
9151 case ISD::VSELECT:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3263 ISD::VSELECT : ISD::SELECT;
3282 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT);
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 274 case ISD::VSELECT: return "vselect";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2345 case ISD::VSELECT: {
5299 !isOperationLegalOrCustom(ISD::VSELECT, VT))
5326 DAG.getNode(ISD::VSELECT, DL, VT, DivisorIsIntMin, MaskedIsZero, Fold);
lib/Target/AArch64/AArch64ISelLowering.cpp 613 setTargetDAGCombine(ISD::VSELECT);
855 setOperationAction(ISD::VSELECT, VT, Expand);
5802 Estimate = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL,
11586 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
11755 case ISD::VSELECT:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 387 setOperationAction(ISD::VSELECT, VT, Expand);
427 setOperationAction(ISD::VSELECT, VT, Expand);
lib/Target/ARM/ARMISelLowering.cpp 182 setOperationAction(ISD::VSELECT, VT, Expand);
7751 DAG.getNode(ISD::VSELECT, dl, MVT::v16i8, RecastV1, AllOnes, AllZeroes);
9014 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru);
lib/Target/Hexagon/HexagonISelLowering.cpp 1518 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
1519 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1567 setTargetDAGCombine(ISD::VSELECT);
2875 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2944 } else if (Opc == ISD::VSELECT) {
2952 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 157 setOperationAction(ISD::VSELECT, T, Custom);
197 setTargetDAGCombine(ISD::VSELECT);
1545 case ISD::VSELECT:
1592 if (Opc == ISD::VSELECT) {
1598 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
lib/Target/Mips/MipsSEISelLowering.cpp 105 setTargetDAGCombine(ISD::VSELECT);
166 setTargetDAGCombine(ISD::VSELECT);
351 setOperationAction(ISD::VSELECT, Ty, Legal);
396 setOperationAction(ISD::VSELECT, Ty, Legal);
710 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
1045 case ISD::VSELECT:
1618 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1633 return DAG.getNode(ISD::VSELECT, DL, VecTy,
1638 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1641 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1645 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1648 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1679 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1684 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
lib/Target/PowerPC/PPCISelLowering.cpp 617 setOperationAction(ISD::VSELECT, VT, Legal);
946 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
994 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1032 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
1150 setTargetDAGCombine(ISD::VSELECT);
14086 case ISD::VSELECT:
15516 assert((N->getOpcode() == ISD::VSELECT) && "Need VSELECT node here");
lib/Target/SystemZ/SystemZISelLowering.cpp 324 setOperationAction(ISD::VSELECT, VT, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 166 for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
lib/Target/X86/X86ISelDAGToDAG.cpp 4453 case ISD::VSELECT: {
lib/Target/X86/X86ISelLowering.cpp 820 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
911 setOperationAction(ISD::VSELECT, VT, Custom);
918 setOperationAction(ISD::VSELECT, VT, Custom);
1053 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1266 setOperationAction(ISD::VSELECT, VT, Custom);
1276 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1347 setOperationAction(ISD::VSELECT, VT, Expand);
1502 setOperationAction(ISD::VSELECT, VT, Custom);
1598 setOperationAction(ISD::VSELECT, VT, Expand);
1669 setOperationAction(ISD::VSELECT, VT, Custom);
1844 setTargetDAGCombine(ISD::VSELECT);
17250 return DAG.getNode(ISD::VSELECT, dl, VT, Cond, LHS, RHS);
17275 SDValue Select = DAG.getNode(ISD::VSELECT, dl, CastVT, Cond, LHS, RHS);
22630 unsigned OpcodeSelect = ISD::VSELECT;
27474 SDValue Select = DAG.getNode(ISD::VSELECT, dl, MaskVT, Mask, NewLoad,
27677 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
36204 if (Vec.getOpcode() == ISD::VSELECT &&
36528 if (N->getOpcode() != ISD::VSELECT)
36633 if (Opcode != X86ISD::BLENDV && Opcode != ISD::VSELECT)
36731 if ((N->getOpcode() != ISD::VSELECT &&
36754 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
36774 if ((UI->getOpcode() != ISD::VSELECT &&
37090 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
37159 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
44529 if (Sel.getOpcode() != ISD::VSELECT ||
44734 if (InOpcode == ISD::VSELECT &&
44908 case ISD::VSELECT: