reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenDAGISel.inc

40867 /* 89670*/  /*SwitchOpcode*/ 9|128,1/*137*/, TARGET_VAL(ISD::VECREDUCE_UMIN),// ->89811

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1615   case ISD::VECREDUCE_UMIN:
19431         ? ISD::VECREDUCE_UMIN : ISD::VECREDUCE_UMAX;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1152   case ISD::VECREDUCE_UMIN:
 3693   case ISD::VECREDUCE_UMIN:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  193   case ISD::VECREDUCE_UMIN:
 1223   case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
 1632   case ISD::VECREDUCE_UMIN:
 1804   case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  473   case ISD::VECREDUCE_UMIN:
  876   case ISD::VECREDUCE_UMIN:

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

  644     case ISD::VECREDUCE_UMIN:
 2046     case ISD::VECREDUCE_UMIN:
 2132   case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
 4184   case ISD::VECREDUCE_UMIN:
 4602   case ISD::VECREDUCE_UMIN:

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 8953     Res = DAG.getNode(ISD::VECREDUCE_UMIN, dl, VT, Op1);

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  439   case ISD::VECREDUCE_UMIN:             return "vecreduce_umin";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 7331   case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break;

lib/CodeGen/TargetLoweringBase.cpp

  744     setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand);

lib/Target/AArch64/AArch64ISelLowering.cpp

  744       setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
 3079   case ISD::VECREDUCE_UMIN:
 8229   case ISD::VECREDUCE_UMIN:
12066   case ISD::VECREDUCE_UMIN:

lib/Target/ARM/ARMISelLowering.cpp

  285     setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);