reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenDAGISel.inc

40819 /* 89525*/  /*SwitchOpcode*/ 13|128,1/*141*/, TARGET_VAL(ISD::VECREDUCE_SMIN),// ->89670

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1613   case ISD::VECREDUCE_SMIN:

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 1150   case ISD::VECREDUCE_SMIN:
 3691   case ISD::VECREDUCE_SMIN:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  191   case ISD::VECREDUCE_SMIN:
 1221   case ISD::VECREDUCE_SMIN:
 1628   case ISD::VECREDUCE_SMIN:
 1802   case ISD::VECREDUCE_SMIN:

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  471   case ISD::VECREDUCE_SMIN:
  874   case ISD::VECREDUCE_SMIN:

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

  642     case ISD::VECREDUCE_SMIN:
 2044     case ISD::VECREDUCE_SMIN:
 2130   case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
 4182   case ISD::VECREDUCE_SMIN:
 4609   case ISD::VECREDUCE_SMIN:

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 8947     Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1);

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  437   case ISD::VECREDUCE_SMIN:             return "vecreduce_smin";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 7329   case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break;

lib/CodeGen/TargetLoweringBase.cpp

  742     setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand);

lib/Target/AArch64/AArch64ISelLowering.cpp

  742       setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
 3077   case ISD::VECREDUCE_SMIN:
 8225   case ISD::VECREDUCE_SMIN:
12064   case ISD::VECREDUCE_SMIN:

lib/Target/ARM/ARMISelLowering.cpp

  284     setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);