reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenDAGISel.inc

37965 /* 83589*/  /*SwitchOpcode*/ 74, TARGET_VAL(ISD::SMUL_LOHI),// ->83666

gen/lib/Target/Sparc/SparcGenDAGISel.inc

 2400 /*  4409*/  /*SwitchOpcode*/ 37, TARGET_VAL(ISD::SMUL_LOHI),// ->4449

include/llvm/CodeGen/TargetLowering.h

 2269     case ISD::SMUL_LOHI:

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1520   case ISD::SMUL_LOHI:          return visitSMUL_LOHI(N);

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3233         Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI;
 3243   case ISD::SMUL_LOHI: {
 3283     bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
 3289       OpToUse = ISD::SMUL_LOHI;
 3293       OpToUse = ISD::SMUL_LOHI;
 4261   case ISD::SMUL_LOHI: {

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 2925   unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

  439   case ISD::SMUL_LOHI:

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  232   case ISD::SMUL_LOHI:                  return "smul_lohi";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 4712   else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT)
 4713                                : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
 4715         DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor);
 5593          Opcode == ISD::SMUL_LOHI);
 5600                       isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
 5620       Lo = DAG.getNode(Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI, dl, VTs, L, R);
 5741   if (!MakeMUL_LOHI(LH, RH, Lo, Hi, Opcode == ISD::SMUL_LOHI))
 5753   if (Opcode == ISD::SMUL_LOHI) {
 7021   unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
 7207         { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};

lib/Target/AArch64/AArch64ISelLowering.cpp

  317   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
  766       setOperationAction(ISD::SMUL_LOHI, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  318     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
  382     setOperationAction(ISD::SMUL_LOHI, VT, Expand);

lib/Target/ARM/ARMISelDAGToDAG.cpp

 3246     if (N->getOperand(1).getOpcode() != ISD::SMUL_LOHI ||

lib/Target/ARM/ARMISelLowering.cpp

  718     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
 1040     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
 4414     Value = DAG.getNode(ISD::SMUL_LOHI, dl,
11139       V->getOpcode() == ISD::SMUL_LOHI)
11275       AddcSubcOp0->getOpcode() != ISD::SMUL_LOHI &&
11277       AddcSubcOp1->getOpcode() != ISD::SMUL_LOHI)
11300   unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
11519   } else if (N->getOperand(1)->getOpcode() == ISD::SMUL_LOHI) {
12079        SRL.getOperand(0).getOpcode() != ISD::SMUL_LOHI)

lib/Target/AVR/AVRISelDAGToDAG.cpp

  477   bool isSigned = N->getOpcode() == ISD::SMUL_LOHI;
  541   case ISD::SMUL_LOHI:  return selectMultiplication(N);

lib/Target/AVR/AVRISelLowering.cpp

  164   setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
  170     setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);

lib/Target/BPF/BPFISelLowering.cpp

   93     setOperationAction(ISD::SMUL_LOHI, VT, Expand);

lib/Target/Hexagon/HexagonISelLowering.cpp

 1377         ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
 1422     ISD::UADDO,   ISD::SSUBO,   ISD::USUBO,   ISD::SMUL_LOHI, ISD::UMUL_LOHI,

lib/Target/Lanai/LanaiISelLowering.cpp

  117   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);

lib/Target/MSP430/MSP430ISelLowering.cpp

  120   setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Promote);
  125   setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);

lib/Target/Mips/Mips16ISelDAGToDAG.cpp

  195   case ISD::SMUL_LOHI:

lib/Target/Mips/MipsSEISelLowering.cpp

  182   setOperationAction(ISD::SMUL_LOHI,          MVT::i32, Custom);
  193     setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Custom);
  229     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  276     setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
  453   case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);

lib/Target/NVPTX/NVPTXISelLowering.cpp

  513   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);

lib/Target/PowerPC/PPCISelLowering.cpp

  263   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  265   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
  652       setOperationAction(ISD::SMUL_LOHI, VT, Expand);

lib/Target/RISCV/RISCVISelLowering.cpp

  129   setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand);

lib/Target/Sparc/SparcISelLowering.cpp

 1654     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
 1670     setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  200       setOperationAction(ISD::SMUL_LOHI, VT, Custom);
 4958   case ISD::SMUL_LOHI:

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  112        {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,

lib/Target/X86/X86ISelDAGToDAG.cpp

 1970   case ISD::SMUL_LOHI:
 4703   case ISD::SMUL_LOHI:
 4709     bool isSigned = Opcode == ISD::SMUL_LOHI;

lib/Target/X86/X86ISelLowering.cpp

  761     setOperationAction(ISD::SMUL_LOHI, VT, Expand);

lib/Target/XCore/XCoreISelLowering.cpp

   97   setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
  209   case ISD::SMUL_LOHI:          return LowerSMUL_LOHI(Op, DAG);
  541   assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&