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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc99028 /*223142*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::SDIV),// ->223169
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7736 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenDAGISel.inc38287 /* 84356*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::SDIV),// ->84403
gen/lib/Target/ARM/ARMGenFastISel.inc 5176 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc16329 /* 30250*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SDIV),// ->30286
26453 /* 50079*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::SDIV),// ->50172
gen/lib/Target/Mips/MipsGenFastISel.inc 3419 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58040 /*123372*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::SDIV),// ->123456
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28482 /* 68462*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::SDIV),// ->68489
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3247 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12203 /* 22711*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::SDIV),// ->22756
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2458 /* 4513*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::SDIV),// ->4555
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc16786 /* 32544*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::SDIV),// ->32571
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1916 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2115 /* 3690*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::SDIV),// ->3703
include/llvm/CodeGen/TargetLowering.h 2304 case ISD::SDIV:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1514 case ISD::SDIV: return visitSDIV(N);
3512 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
3531 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
3536 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3568 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
3584 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
3640 return DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, N0C, N1C);
3931 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
19602 if (Opcode != ISD::UDIV && Opcode != ISD::SDIV &&
lib/CodeGen/SelectionDAG/FastISel.cpp 634 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
1811 return selectBinaryOp(I, ISD::SDIV);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3200 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3218 case ISD::SDIV: {
3219 bool isSigned = Node->getOpcode() == ISD::SDIV;
4063 case ISD::SDIV:
4223 case ISD::SDIV:
4241 case ISD::SDIV:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 133 case ISD::SDIV:
1706 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 364 case ISD::SDIV:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 135 case ISD::SDIV:
941 case ISD::SDIV:
2761 case ISD::SDIV:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4724 case ISD::SDIV:
4771 case ISD::SDIV:
5105 case ISD::SDIV:
5379 case ISD::SDIV:
5401 case ISD::SDIV:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3192 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 228 case ISD::SDIV: return "sdiv";
lib/CodeGen/TargetLoweringBase.cpp 811 case ISD::SDIV:
1599 case SDiv: return ISD::SDIV;
lib/Target/AArch64/AArch64FastISel.cpp 4925 return selectBinaryOp(I, ISD::SDIV);
4930 return selectBinaryOp(I, ISD::SDIV);
lib/Target/AArch64/AArch64ISelLowering.cpp 864 setOperationAction(ISD::SDIV, VT, Expand);
lib/Target/AArch64/AArch64TargetTransformInfo.cpp 501 case ISD::SDIV:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 308 setOperationAction(ISD::SDIV, VT, Expand);
378 setOperationAction(ISD::SDIV, VT, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 447 setOperationAction(ISD::SDIV, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 201 setOperationAction(ISD::SDIV, VT, Expand);
275 setOperationAction(ISD::SDIV, VT, Expand);
839 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
840 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
1097 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1102 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1105 setOperationAction(ISD::SDIV, MVT::i64, Custom);
8846 if (N->getOpcode() != ISD::SDIV)
9201 case ISD::SDIV:
9312 case ISD::SDIV:
9314 return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
15979 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
lib/Target/ARM/ARMTargetTransformInfo.cpp 658 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
662 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
666 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
670 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
675 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
679 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
683 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
687 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
915 case ISD::SDIV:
lib/Target/AVR/AVRISelLowering.cpp 148 setOperationAction(ISD::SDIV, MVT::i8, Expand);
149 setOperationAction(ISD::SDIV, MVT::i16, Expand);
lib/Target/BPF/BPFISelDAGToDAG.cpp 192 case ISD::SDIV: {
lib/Target/Hexagon/HexagonISelLowering.cpp 1374 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1420 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
lib/Target/Lanai/LanaiISelLowering.cpp 106 setOperationAction(ISD::SDIV, MVT::i32, Expand);
lib/Target/Lanai/LanaiTargetTransformInfo.h 92 case ISD::SDIV:
lib/Target/MSP430/MSP430ISelLowering.cpp 131 setOperationAction(ISD::SDIV, MVT::i8, Promote);
137 setOperationAction(ISD::SDIV, MVT::i16, LibCall);
lib/Target/Mips/MipsFastISel.cpp 1931 case ISD::SDIV:
2046 if (!selectBinaryOp(I, ISD::SDIV))
2047 return selectDivRem(I, ISD::SDIV);
lib/Target/Mips/MipsISelLowering.cpp 393 setOperationAction(ISD::SDIV, MVT::i32, Expand);
397 setOperationAction(ISD::SDIV, MVT::i64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 239 setOperationAction(ISD::SDIV, MVT::i32, Legal);
286 setOperationAction(ISD::SDIV, MVT::i64, Legal);
338 setOperationAction(ISD::SDIV, Ty, Legal);
1810 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 4552 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV;
lib/Target/PowerPC/PPCISelLowering.cpp 625 setOperationAction(ISD::SDIV, VT, Expand);
9544 if ((Op.getOpcode() == ISD::SREM && UI->getOpcode() == ISD::SDIV) ||
lib/Target/RISCV/RISCVISelLowering.cpp 114 setOperationAction(ISD::SDIV, XLenVT, Expand);
122 setOperationAction(ISD::SDIV, MVT::i32, Custom);
824 case ISD::SDIV:
898 case ISD::SDIV:
lib/Target/Sparc/SparcISelDAGToDAG.cpp 341 case ISD::SDIV:
352 if (N->getOpcode() == ISD::SDIV) {
364 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
lib/Target/Sparc/SparcISelLowering.cpp 1658 setOperationAction(ISD::SDIV, MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 159 setOperationAction(ISD::SDIV, VT, Expand);
617 setTargetDAGCombine(ISD::SDIV);
6174 case ISD::SDIV:
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 175 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
lib/Target/X86/X86ISelLowering.cpp 312 setOperationAction(ISD::SDIV, VT, Expand);
747 setOperationAction(ISD::SDIV, VT, Expand);
848 setOperationAction(ISD::SDIV, VT, Custom);
1816 setOperationAction(ISD::SDIV, MVT::i128, Custom);
25393 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
27937 case ISD::SDIV:
lib/Target/X86/X86TargetTransformInfo.cpp 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
252 if (ISD == ISD::SDIV || ISD == ISD::SREM) {
349 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
353 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence
368 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence
383 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence
387 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
391 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
405 { ISD::SDIV, MVT::v32i8, 28+2 }, // 4*ext+4*pmulhw sequence + split.
407 { ISD::SDIV, MVT::v16i8, 14 }, // 2*ext+2*pmulhw sequence
413 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
415 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
421 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split.
423 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
435 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
439 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
876 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM ||