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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc105501 /*236025*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSUB),
105545 /*236104*/ OPC_CheckOpcode, TARGET_VAL(ISD::FSUB),
106386 /*237689*/ /*SwitchOpcode*/ 100, TARGET_VAL(ISD::FSUB),// ->237792
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7730 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc74216 /*164139*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::FSUB),// ->164222
gen/lib/Target/ARM/ARMGenDAGISel.inc42785 /* 94242*/ /*SwitchOpcode*/ 43|128,14/*1835*/, TARGET_VAL(ISD::FSUB),// ->96081
gen/lib/Target/ARM/ARMGenFastISel.inc 5170 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68463 /*132594*/ /*SwitchOpcode*/ 26, TARGET_VAL(ISD::FSUB),// ->132623
gen/lib/Target/Mips/MipsGenDAGISel.inc26717 /* 50577*/ /*SwitchOpcode*/ 7|128,3/*391*/, TARGET_VAL(ISD::FSUB),// ->50972
26784 /* 50706*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::FSUB),// ->50761
27019 /* 51147*/ /*SwitchOpcode*/ 79, TARGET_VAL(ISD::FSUB),// ->51229
gen/lib/Target/Mips/MipsGenFastISel.inc 3413 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc70299 /*148321*/ /*SwitchOpcode*/ 16|128,2/*272*/, TARGET_VAL(ISD::FSUB),// ->148597
gen/lib/Target/PowerPC/PPCGenDAGISel.inc38012 /* 96644*/ /*SwitchOpcode*/ 23|128,1/*151*/, TARGET_VAL(ISD::FSUB),// ->96799
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3242 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13444 /* 25134*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FSUB),// ->25239
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3239 /* 5983*/ /*SwitchOpcode*/ 36, TARGET_VAL(ISD::FSUB),// ->6022
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc23597 /* 44469*/ /*SwitchOpcode*/ 30|128,1/*158*/, TARGET_VAL(ISD::FSUB),// ->44631
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18904 /* 36092*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::FSUB),// ->36143
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1910 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc62903 /*132886*/ /*SwitchOpcode*/ 29|128,11/*1437*/, TARGET_VAL(ISD::FSUB),// ->134327
130727 /*268410*/ /*SwitchOpcode*/ 3|128,1/*131*/, TARGET_VAL(ISD::FSUB),// ->268545
136314 /*279662*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::FSUB),// ->279795
141631 /*290399*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FSUB),// ->290436
143524 /*293990*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FSUB),// ->294027
150027 /*306315*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::FSUB),// ->306394
153341 /*312647*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::FSUB),// ->312724
156659 /*318959*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FSUB),// ->318981
157942 /*321307*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FSUB),// ->321328
164521 /*333827*/ /*SwitchOpcode*/ 3|128,1/*131*/, TARGET_VAL(ISD::FSUB),// ->333962
169821 /*344522*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::FSUB),// ->344655
174647 /*354376*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FSUB),// ->354413
175971 /*356906*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::FSUB),// ->356943
181187 /*366963*/ /*SwitchOpcode*/ 2|128,1/*130*/, TARGET_VAL(ISD::FSUB),// ->367097
185488 /*375181*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::FSUB),// ->375203
186192 /*376458*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::FSUB),// ->376479
233559 /*476281*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FSUB),// ->476377
235039 /*479393*/ /*SwitchOpcode*/ 85, TARGET_VAL(ISD::FSUB),// ->479481
236721 /*482910*/ /*SwitchOpcode*/ 87, TARGET_VAL(ISD::FSUB),// ->483000
237727 /*485070*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::FSUB),// ->485155
239991 /*489811*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FSUB),// ->489907
241471 /*492923*/ /*SwitchOpcode*/ 85, TARGET_VAL(ISD::FSUB),// ->493011
243238 /*496617*/ /*SwitchOpcode*/ 87, TARGET_VAL(ISD::FSUB),// ->496707
244245 /*498779*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::FSUB),// ->498864
gen/lib/Target/X86/X86GenFastISel.inc13516 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 942 case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
2308 case ISD::FSUB:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1563 case ISD::FSUB: return visitFSUB(N);
11888 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) {
11952 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
11955 ISD::FSUB, DL, VT, N0,
11959 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
11962 ISD::FSUB, DL, VT, N1,
11976 return DAG.getNode(ISD::FSUB, DL, VT, N1, Add, Flags);
11982 return DAG.getNode(ISD::FSUB, DL, VT, N0, Add, Flags);
12115 return DAG.getNode(ISD::FSUB, DL, VT, N0, N1, Flags);
20304 NewEst = DAG.getNode(ISD::FSUB, DL, VT,
20342 HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg, Flags);
20348 NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst, Flags);
lib/CodeGen/SelectionDAG/FastISel.cpp 1804 return selectBinaryOp(I, ISD::FSUB);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2397 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
3081 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3173 case ISD::FSUB: {
4046 case ISD::FSUB:
4347 case ISD::FSUB:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 96 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
1166 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
2083 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 371 case ISD::FSUB:
792 case ISD::FSUB:
1248 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1252 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 132 case ISD::FSUB:
935 case ISD::FSUB:
2758 case ISD::FSUB:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3998 case ISD::FSUB:
4655 OpOpcode == ISD::FSUB)
4656 return getNode(ISD::FSUB, DL, VT, Operand.getOperand(1),
4992 case ISD::FSUB:
5022 case ISD::FSUB:
5120 case ISD::FSUB:
7167 if (Opcode == ISD::FSUB)
7755 case ISD::STRICT_FSUB: NewOpc = ISD::FSUB; break;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 2972 visitBinary(I, ISD::FSUB);
4905 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
5042 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5059 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5065 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5084 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5090 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5096 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5138 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5155 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5161 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5181 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5187 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
5193 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
5237 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
5250 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5256 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5271 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
5277 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
5283 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 248 case ISD::FSUB: return "fsub";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2482 case ISD::FSUB:
5394 if (LegalOperations && !isOperationLegalOrCustom(ISD::FSUB, VT))
5404 case ISD::FSUB:
5497 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
5503 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
5508 case ISD::FSUB:
5516 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
6005 SrcBiased = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst);
6026 DAG.getNode(ISD::FSUB, dl, SrcVT, Src, Cst));
6089 !isOperationLegalOrCustom(ISD::FSUB, DstVT) ||
6111 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, DstVT, HiFlt, TwoP84PlusTwoP52);
lib/CodeGen/TargetLoweringBase.cpp 1595 case FSub: return ISD::FSUB;
lib/Target/AArch64/AArch64ISelLowering.cpp 251 setOperationAction(ISD::FSUB, MVT::f128, Custom);
402 setOperationAction(ISD::FSUB, MVT::f16, Promote);
422 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
428 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
463 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
680 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
3010 case ISD::FSUB:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 276 setOperationAction(ISD::FSUB, MVT::f64, Expand);
425 setOperationAction(ISD::FSUB, VT, Expand);
501 setTargetDAGCombine(ISD::FSUB);
517 case ISD::FSUB:
2030 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
2135 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2170 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 392 case ISD::FSUB:
lib/Target/AMDGPU/R600ISelLowering.cpp 150 setOperationAction(ISD::FSUB, MVT::f32, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 705 setTargetDAGCombine(ISD::FSUB);
8565 case ISD::FSUB:
8734 case ISD::FSUB:
9284 case ISD::FSUB:
9949 case ISD::FSUB:
lib/Target/ARM/ARMFastISel.cpp 1815 case ISD::FSUB:
2853 return SelectBinaryFPOp(I, ISD::FSUB);
lib/Target/ARM/ARMISelLowering.cpp 764 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
937 setOperationAction(ISD::FSUB, MVT::f64, Expand);
11802 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
11805 Opcode != ISD::FADD && Opcode != ISD::FSUB)
lib/Target/Hexagon/HexagonISelLowering.cpp 1427 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1527 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1564 setOperationAction(ISD::FSUB, MVT::f64, Legal);
lib/Target/Mips/MipsSEISelLowering.cpp 132 setOperationAction(ISD::FSUB, MVT::f16, Promote);
395 setOperationAction(ISD::FSUB, Ty, Legal);
1924 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 536 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
lib/Target/PowerPC/PPCISelLowering.cpp 884 setOperationAction(ISD::FSUB, MVT::f128, Legal);
931 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
982 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
7309 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
7319 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
7325 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags);
7331 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
7337 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags);
7472 SDValue True = DAG.getNode(ISD::FSUB, dl, MVT::ppcf128,
10077 case ISD::FSUB: {
lib/Target/Sparc/SparcISelLowering.cpp 1712 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1737 setOperationAction(ISD::FSUB, MVT::f128, Custom);
3040 case ISD::FSUB: return LowerF128Op(Op, DAG,
lib/Target/SystemZ/SystemZISelLowering.cpp 474 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
506 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
lib/Target/X86/X86ISelLowering.cpp 541 setOperationAction(ISD::FSUB, VT, Custom);
672 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1853 setTargetDAGCombine(ISD::FSUB);
8779 if (Opcode != ISD::FADD && Opcode != ISD::FSUB)
8820 if (Opcode == ISD::FSUB)
8974 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break;
9158 else if (isHorizontalBinOpPart(BV, ISD::FSUB, DAG, 0, NumElts, InVec0,
18591 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
18637 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
18986 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
19685 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break;
27710 case ISD::FSUB: return lowerFaddFsub(Op, DAG);
28235 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
33591 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB ||
33855 if ((V1.getOpcode() != ISD::FADD && V1.getOpcode() != ISD::FSUB) ||
33856 (V2.getOpcode() != ISD::FADD && V2.getOpcode() != ISD::FSUB) ||
33867 if (V1.getOpcode() == ISD::FSUB) {
33873 assert(V2.getOpcode() == ISD::FSUB && "Unexpected opcode");
36227 case ISD::FSUB:
40920 assert((IsFadd || N->getOpcode() == ISD::FSUB) && "Wrong opcode");
41459 if (Opc != X86ISD::FXOR && Opc != ISD::XOR && Opc != ISD::FSUB)
41468 if (Opc == ISD::FSUB)
44935 case ISD::FSUB: return combineFaddFsub(N, DAG, Subtarget);
lib/Target/X86/X86IntrinsicsInfo.h 921 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
922 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
lib/Target/X86/X86TargetTransformInfo.cpp 208 { ISD::FSUB, MVT::v2f64, 2 }, // subpd
543 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/
547 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/
696 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/
697 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/
756 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/
757 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/
758 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/
759 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/
839 { ISD::FSUB, MVT::f32, 2 }, // Pentium IV from http://www.agner.org/
840 { ISD::FSUB, MVT::f64, 2 }, // Pentium IV from http://www.agner.org/
854 { ISD::FSUB, MVT::f32, 1 }, // Pentium III from http://www.agner.org/
855 { ISD::FSUB, MVT::v4f32, 2 }, // Pentium III from http://www.agner.org/