|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc106329 /*237576*/ /*SwitchOpcode*/ 110, TARGET_VAL(ISD::FMINIMUM),// ->237689
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7727 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/ARM/ARMGenDAGISel.inc45380 /*100522*/ /*SwitchOpcode*/ 28|128,2/*284*/, TARGET_VAL(ISD::FMINIMUM),// ->100810
gen/lib/Target/ARM/ARMGenFastISel.inc 5167 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc25682 /* 48822*/ /*SwitchOpcode*/ 84, TARGET_VAL(ISD::FMINIMUM),// ->48909
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc19091 /* 36454*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::FMINIMUM),// ->36505
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1908 case ISD::FMINIMUM: return fastEmit_ISD_FMINIMUM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/BasicTTIImpl.h 1241 ISDs.push_back(ISD::FMINIMUM);
include/llvm/CodeGen/TargetLowering.h 2286 case ISD::FMINIMUM:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1582 case ISD::FMINIMUM: return visitFMINIMUM(N);
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 2077 case ISD::FMINIMUM:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 409 case ISD::FMINIMUM:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 118 case ISD::FMINIMUM:
939 case ISD::FMINIMUM:
2137 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
2742 case ISD::FMINIMUM:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4076 case ISD::FMINIMUM:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3295 case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break;
3300 else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT))
3301 Opc = ISD::FMINIMUM;
3304 ISD::FMINNUM : ISD::FMINIMUM;
6085 setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 188 case ISD::FMINIMUM: return "fminimum";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6149 Node->getOpcode() == ISD::FMINNUM ? ISD::FMINIMUM : ISD::FMAXIMUM;
7336 BaseOpcode = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
lib/CodeGen/TargetLoweringBase.cpp 639 setOperationAction(ISD::FMINIMUM, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 417 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
482 setOperationAction(ISD::FMINIMUM, Ty, Legal);
499 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
884 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM})
10495 return DAG.getNode(ISD::FMINIMUM, SDLoc(N), N->getValueType(0),
lib/Target/ARM/ARMISelLowering.cpp 1391 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1393 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1395 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1397 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1406 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1408 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
3737 ? ISD::FMINIMUM : ISD::FMAXIMUM;
lib/Target/Mips/MipsSEISelLowering.cpp 160 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
lib/Target/NVPTX/NVPTXISelLowering.cpp 580 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
lib/Target/SystemZ/SystemZISelLowering.cpp 522 setOperationAction(ISD::FMINIMUM, MVT::f64, Legal);
527 setOperationAction(ISD::FMINIMUM, MVT::v2f64, Legal);
532 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
537 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
542 setOperationAction(ISD::FMINIMUM, MVT::f128, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 101 setOperationAction(ISD::FMINIMUM, T, Legal);
lib/Target/X86/X86ISelLowering.cpp36237 case ISD::FMINIMUM: