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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc83077 /*192773*/ /*SwitchOpcode*/ 120|128,1/*248*/, TARGET_VAL(ISD::CTLZ),// ->193025
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4274 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/ARM/ARMGenDAGISel.inc38329 /* 84450*/ /*SwitchOpcode*/ 127|128,1/*255*/, TARGET_VAL(ISD::CTLZ),// ->84709
gen/lib/Target/ARM/ARMGenFastISel.inc 2709 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc63937 /*122664*/ OPC_SwitchOpcode /*2 cases */, 46, TARGET_VAL(ISD::CTLZ),// ->122714
65216 /*125379*/ /*SwitchOpcode*/ 65|128,3/*449*/, TARGET_VAL(ISD::CTLZ),// ->125832
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 1272 /* 2313*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::CTLZ),// ->2324
gen/lib/Target/Mips/MipsGenDAGISel.inc12148 /* 22650*/ /*SwitchOpcode*/ 75|128,1/*203*/, TARGET_VAL(ISD::CTLZ),// ->22857
gen/lib/Target/Mips/MipsGenFastISel.inc 1196 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc68419 /*144682*/ OPC_SwitchOpcode /*2 cases */, 13, TARGET_VAL(ISD::CTLZ),// ->144699
68548 /*144946*/ /*SwitchOpcode*/ 37, TARGET_VAL(ISD::CTLZ),// ->144986
69431 /*146706*/ /*SwitchOpcode*/ 80, TARGET_VAL(ISD::CTLZ),// ->146789
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28274 /* 68089*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::CTLZ),// ->68169
gen/lib/Target/PowerPC/PPCGenFastISel.inc 1696 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc22060 /* 41447*/ /*SwitchOpcode*/ 78, TARGET_VAL(ISD::CTLZ),// ->41528
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc18381 /* 35224*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::CTLZ),// ->35252
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 961 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc37791 /* 79084*/ /*SwitchOpcode*/ 47|128,5/*687*/, TARGET_VAL(ISD::CTLZ),// ->79775
80052 /*168011*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::CTLZ),// ->168091
85008 /*178049*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::CTLZ),// ->178127
90719 /*189146*/ /*SwitchOpcode*/ 9|128,1/*137*/, TARGET_VAL(ISD::CTLZ),// ->189287
96815 /*201622*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(ISD::CTLZ),// ->201759
103838 /*215373*/ /*SwitchOpcode*/ 9|128,1/*137*/, TARGET_VAL(ISD::CTLZ),// ->215514
110994 /*230151*/ /*SwitchOpcode*/ 5|128,1/*133*/, TARGET_VAL(ISD::CTLZ),// ->230288
117295 /*242403*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::CTLZ),// ->242536
125377 /*257926*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::CTLZ),// ->257970
127698 /*262495*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::CTLZ),// ->262537
146274 /*299065*/ OPC_CheckOpcode, TARGET_VAL(ISD::CTLZ),
148088 /*302592*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::CTLZ),// ->302613
160236 /*325460*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::CTLZ),// ->325504
161886 /*328684*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::CTLZ),// ->328726
177779 /*360309*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::CTLZ),// ->360331
178664 /*361976*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::CTLZ),// ->361997
gen/lib/Target/X86/X86GenFastISel.inc 5908 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2149 /* 3753*/ /*SwitchOpcode*/ 8, TARGET_VAL(ISD::CTLZ),// ->3764
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1541 case ISD::CTLZ: return visitCTLZ(N);
7847 if (N1C && N0.getOpcode() == ISD::CTLZ &&
8059 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
20164 if ((Count.getOpcode() == ISD::CTLZ ||
20167 (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT)))
20168 return DAG.getNode(ISD::CTLZ, DL, VT, N0);
20251 SDValue Ctlz = DAG.getNode(ISD::CTLZ, DL, VT, V);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2668 case ISD::CTLZ:
4140 case ISD::CTLZ:
4157 if (Node->getOpcode() == ISD::CTLZ ||
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
1694 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 388 case ISD::CTLZ:
802 case ISD::CTLZ:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 75 case ISD::CTLZ:
887 case ISD::CTLZ:
2018 case ISD::CTLZ:
2888 case ISD::CTLZ:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2903 case ISD::CTLZ:
4332 case ISD::CTLZ:
4445 case ISD::CTLZ:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6214 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 389 case ISD::CTLZ: return "ctlz";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3087 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
6229 isOperationLegalOrCustom(ISD::CTLZ, VT)) {
6230 Result = DAG.getNode(ISD::CTLZ, dl, VT, Op);
6301 !isOperationLegalOrCustom(ISD::CTLZ, VT)) ||
6316 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
6319 DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
6873 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
lib/Target/AArch64/AArch64ISelLowering.cpp 727 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
728 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 323 setOperationAction(ISD::CTLZ, VT, Expand);
353 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
393 setOperationAction(ISD::CTLZ, VT, Expand);
1158 case ISD::CTLZ:
2308 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
lib/Target/AMDGPU/SIISelLowering.cpp 457 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 264 setOperationAction(ISD::CTLZ, VT, Legal);
869 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
870 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
1078 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
3645 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3665 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3672 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
5917 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5942 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
14317 Res = DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::CTLZ, dl, VT, Sub),
lib/Target/AVR/AVRISelLowering.cpp 181 setOperationAction(ISD::CTLZ, VT, Expand);
lib/Target/BPF/BPFISelLowering.cpp 113 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
lib/Target/Hexagon/HexagonISelLowering.cpp 1352 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1353 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1425 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 82 setOperationAction(ISD::CTLZ, T, Legal);
144 setOperationAction(ISD::CTLZ, T, Custom);
1263 {VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)});
1533 case ISD::CTLZ:
lib/Target/Lanai/LanaiISelLowering.cpp 127 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
lib/Target/MSP430/MSP430ISelLowering.cpp 102 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
103 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
lib/Target/Mips/MipsISelLowering.cpp 482 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
484 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 334 setOperationAction(ISD::CTLZ, Ty, Legal);
2084 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
lib/Target/NVPTX/NVPTXISelLowering.cpp 502 setOperationAction(ISD::CTLZ, Ty, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 589 setOperationAction(ISD::CTLZ, VT, Legal);
593 setOperationAction(ISD::CTLZ, VT, Expand);
lib/Target/RISCV/RISCVISelLowering.cpp 140 setOperationAction(ISD::CTLZ, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1568 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1632 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 257 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
259 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
353 setOperationAction(ISD::CTLZ, VT, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 175 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
lib/Target/X86/X86ISelLowering.cpp 355 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
358 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
359 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
360 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
365 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
769 setOperationAction(ISD::CTLZ, VT, Expand);
1018 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1019 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1020 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1021 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1173 setOperationAction(ISD::CTLZ, VT, Custom);
1482 setOperationAction(ISD::CTLZ, VT, Legal);
1577 setOperationAction(ISD::CTLZ, VT, Legal);
1677 setOperationAction(ISD::CTLZ, VT, Custom);
24631 assert(Op.getOpcode() == ISD::CTLZ);
24651 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
24785 if (Opc == ISD::CTLZ) {
27742 case ISD::CTLZ:
39495 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Cmp->getOperand(0));
lib/Target/X86/X86TargetTransformInfo.cpp 1887 { ISD::CTLZ, MVT::v8i64, 1 },
1888 { ISD::CTLZ, MVT::v16i32, 1 },
1889 { ISD::CTLZ, MVT::v32i16, 8 },
1890 { ISD::CTLZ, MVT::v64i8, 20 },
1891 { ISD::CTLZ, MVT::v4i64, 1 },
1892 { ISD::CTLZ, MVT::v8i32, 1 },
1893 { ISD::CTLZ, MVT::v16i16, 4 },
1894 { ISD::CTLZ, MVT::v32i8, 10 },
1895 { ISD::CTLZ, MVT::v2i64, 1 },
1896 { ISD::CTLZ, MVT::v4i32, 1 },
1897 { ISD::CTLZ, MVT::v8i16, 4 },
1898 { ISD::CTLZ, MVT::v16i8, 4 },
1905 { ISD::CTLZ, MVT::v8i64, 23 },
1906 { ISD::CTLZ, MVT::v16i32, 22 },
1907 { ISD::CTLZ, MVT::v32i16, 18 },
1908 { ISD::CTLZ, MVT::v64i8, 17 },
1929 { ISD::CTLZ, MVT::v8i64, 29 },
1930 { ISD::CTLZ, MVT::v16i32, 35 },
1966 { ISD::CTLZ, MVT::v4i64, 23 },
1967 { ISD::CTLZ, MVT::v8i32, 18 },
1968 { ISD::CTLZ, MVT::v16i16, 14 },
1969 { ISD::CTLZ, MVT::v32i8, 9 },
2003 { ISD::CTLZ, MVT::v4i64, 48 }, // 2 x 128-bit Op + extract/insert
2004 { ISD::CTLZ, MVT::v8i32, 38 }, // 2 x 128-bit Op + extract/insert
2005 { ISD::CTLZ, MVT::v16i16, 30 }, // 2 x 128-bit Op + extract/insert
2006 { ISD::CTLZ, MVT::v32i8, 20 }, // 2 x 128-bit Op + extract/insert
2058 { ISD::CTLZ, MVT::v2i64, 23 },
2059 { ISD::CTLZ, MVT::v4i32, 18 },
2060 { ISD::CTLZ, MVT::v8i16, 14 },
2061 { ISD::CTLZ, MVT::v16i8, 9 },
2079 { ISD::CTLZ, MVT::v2i64, 25 },
2080 { ISD::CTLZ, MVT::v4i32, 26 },
2081 { ISD::CTLZ, MVT::v8i16, 20 },
2082 { ISD::CTLZ, MVT::v16i8, 17 },
2107 { ISD::CTLZ, MVT::i64, 1 },
2110 { ISD::CTLZ, MVT::i32, 1 },
2111 { ISD::CTLZ, MVT::i16, 1 },
2112 { ISD::CTLZ, MVT::i8, 1 },
2124 { ISD::CTLZ, MVT::i64, 4 }, // BSR+XOR or BSR+XOR+CMOV
2133 { ISD::CTLZ, MVT::i32, 4 }, // BSR+XOR or BSR+XOR+CMOV
2134 { ISD::CTLZ, MVT::i16, 4 }, // BSR+XOR or BSR+XOR+CMOV
2135 { ISD::CTLZ, MVT::i8, 4 }, // BSR+XOR or BSR+XOR+CMOV
2159 ISD = ISD::CTLZ;