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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc108205 /*241579*/ /*SwitchOpcode*/ 126|128,23/*3070*/, TARGET_VAL(ISD::CONCAT_VECTORS),// ->244653
gen/lib/Target/ARM/ARMGenDAGISel.inc53263 /*119032*/ /*SwitchOpcode*/ 20|128,1/*148*/, TARGET_VAL(ISD::CONCAT_VECTORS),// ->119184
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc70267 /*136313*/ /*SwitchOpcode*/ 15|128,3/*399*/, TARGET_VAL(ISD::CONCAT_VECTORS),// ->136716
gen/lib/Target/X86/X86GenDAGISel.inc231647 /*472487*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::CONCAT_VECTORS),// ->472538
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1593 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
8519 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
8520 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
8560 ISD::CONCAT_VECTORS, DL, VT,
8780 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
8781 N2.getOpcode() == ISD::CONCAT_VECTORS &&
9138 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads);
10723 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
10759 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
15155 StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS
15188 StoredVal = DAG.getNode(MemVT.isVector() ? ISD::CONCAT_VECTORS
16579 SDValue PaddedSubV = DAG.getNode(ISD::CONCAT_VECTORS, DL, ShufVT, ConcatOps);
17195 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
17239 VecIn2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
17649 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N),
17861 if (In.getOpcode() == ISD::CONCAT_VECTORS && In.hasOneUse()) {
17865 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
18025 if (IndexC && V.getOpcode() == ISD::CONCAT_VECTORS &&
18156 if (V.getOpcode() == ISD::CONCAT_VECTORS && V.getNumOperands() == 2)
18278 if (V.getOpcode() == ISD::CONCAT_VECTORS && isa<ConstantSDNode>(Index) &&
18368 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
18369 N1.getOpcode() != ISD::CONCAT_VECTORS || N1.getNumOperands() != 2 ||
18405 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Shuf0, Shuf1);
18436 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1);
18470 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
18983 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
18986 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
19369 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() &&
19376 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
19643 return Concat.getOpcode() == ISD::CONCAT_VECTORS &&
19670 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2943 case ISD::CONCAT_VECTORS:
4430 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4552 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 105 case ISD::CONCAT_VECTORS:
939 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1164 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 613 case ISD::CONCAT_VECTORS:
851 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
1142 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
1145 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
1441 ISD::CONCAT_VECTORS, dl, OtherVT,
1984 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
2104 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
2179 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
2284 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
2352 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
2613 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
2641 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2676 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2711 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2994 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
3014 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3304 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
3560 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
3611 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
3818 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
3885 Mask = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubOps);
4145 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
4809 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
4844 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
4886 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
4895 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
4909 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
5099 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 2535 case ISD::CONCAT_VECTORS: {
3834 case ISD::CONCAT_VECTORS: {
4462 case ISD::CONCAT_VECTORS:
5071 case ISD::CONCAT_VECTORS: {
5244 N1.getOpcode() == ISD::CONCAT_VECTORS &&
5345 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS &&
5473 case ISD::CONCAT_VECTORS: {
7220 case ISD::CONCAT_VECTORS:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 418 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
3613 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps));
3631 Src1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1);
3632 Src2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2);
5409 case ISD::CONCAT_VECTORS:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 278 case ISD::CONCAT_VECTORS: return "concat_vectors";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 928 case ISD::CONCAT_VECTORS: {
2243 case ISD::CONCAT_VECTORS: {
lib/CodeGen/TargetLoweringBase.cpp 634 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 605 setTargetDAGCombine(ISD::CONCAT_VECTORS);
851 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
2916 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16,
6353 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
6742 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
6880 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
6888 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
6964 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
10046 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
10621 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
11751 case ISD::CONCAT_VECTORS:
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 278 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3i32, Custom);
279 setOperationAction(ISD::CONCAT_VECTORS, MVT::v3f32, Custom);
280 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
281 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
282 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5i32, Custom);
283 setOperationAction(ISD::CONCAT_VECTORS, MVT::v5f32, Custom);
284 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
285 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1134 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
1440 Join = DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad);
lib/Target/AMDGPU/SIISelLowering.cpp 264 case ISD::CONCAT_VECTORS:
522 case ISD::CONCAT_VECTORS:
3963 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3986 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4009 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4956 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
5699 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads);
lib/Target/ARM/ARMISelLowering.cpp 178 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
392 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
7290 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper);
7426 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
7907 if (ST->hasNEON() && V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
7925 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
8595 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
8632 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
9198 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG, Subtarget);
11029 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT,
12830 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
12831 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
12847 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
13888 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ToVT, NewLoad1, NewLoad2);
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 1429 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1});
lib/Target/Hexagon/HexagonISelLowering.cpp 1439 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1484 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
2844 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 96 setOperationAction(ISD::CONCAT_VECTORS, T, Custom);
130 setOperationAction(ISD::CONCAT_VECTORS, T, Custom);
187 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom);
254 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)),
902 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1});
903 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV});
949 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1});
950 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV});
1037 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
1105 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy,
1107 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy,
1470 SDValue S = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, L, H);
1503 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1),
1557 case ISD::CONCAT_VECTORS: return LowerHvxConcatVectors(Op, DAG);
lib/Target/NVPTX/NVPTXISelLowering.cpp 2188 case ISD::CONCAT_VECTORS:
lib/Target/PowerPC/PPCISelLowering.cpp 950 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
998 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
1039 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
7647 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops);
lib/Target/X86/X86ISelLowering.cpp 1271 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1342 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1613 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1614 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1644 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1645 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1840 setTargetDAGCombine(ISD::CONCAT_VECTORS);
2778 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
5573 if (N->getOpcode() == ISD::CONCAT_VECTORS) {
5646 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Subs);
5886 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(V), V.getValueType(), CatOps);
8553 DstVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, ImmL, ImmH);
8741 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
9392 ISD::CONCAT_VECTORS, DL, VT,
9398 SDValue LoLo = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Lo);
9399 SDValue HiHi = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Hi, Hi);
9980 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
9982 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
9984 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
10069 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
10071 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT,
10073 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
12533 case ISD::CONCAT_VECTORS: {
14627 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
15163 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Op0, Op1);
18434 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
18653 N0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
19057 In = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op),
19084 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpLo);
19092 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
19105 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i16, Lo, Hi);
19285 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, PackedVT, Lo, Hi);
19342 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
19392 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
19555 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32, Src,
19621 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
20512 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
21283 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
21656 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
21730 In = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op),
21757 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
21878 StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, StoredVal,
22609 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
24602 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
24847 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
24876 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
26774 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
26786 return DAG.getNode(ISD::CONCAT_VECTORS, dl, DstVT, Lo, Hi);
26814 Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT, Src,
27354 if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
27407 Src = DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Src, DAG.getUNDEF(VT));
27675 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
27862 Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i8, ConcatOps);
27889 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWideVT, Ops);
27891 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWideVT, Ops);
27930 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
27932 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
27954 SDValue N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Ops0);
28013 In = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i64, In,
28073 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
28111 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
28150 Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatVT, ConcatOps);
28462 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, DstVT, Lo, Hi);
28491 SDValue PassThru = DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT,
28497 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i1, Mask,
33995 if (N0.getOpcode() != ISD::CONCAT_VECTORS ||
33996 N1.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
34011 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, N0.getOperand(0),
35515 if (N0.getOpcode() == ISD::CONCAT_VECTORS) {
35522 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
35531 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
35623 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i32, N0,
35728 SDValue SadOp0 = DAG.getNode(ISD::CONCAT_VECTORS, DL, ExtendedVT, Ops);
35730 SDValue SadOp1 = DAG.getNode(ISD::CONCAT_VECTORS, DL, ExtendedVT, Ops);
36301 Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i8, Rdx,
36307 Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, Rdx,
37927 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ResLo, ResHi);
38499 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v16i32,
39136 if (Src.getOpcode() != ISD::CONCAT_VECTORS)
39164 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT,
40048 SatVal = DAG.getNode(ISD::CONCAT_VECTORS, DL, InVT, ConcatOps);
40242 SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2);
40527 StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
43745 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Madd, Zero);
43816 Sad = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Ops);
44341 DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Src),
44352 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8f32, Src);
44369 DAG.getNode(ISD::CONCAT_VECTORS, DL, SrcVT, LHS),
44370 DAG.getNode(ISD::CONCAT_VECTORS, DL, SrcVT, RHS));
44609 return peekThroughBitcasts(NotOp).getOpcode() == ISD::CONCAT_VECTORS;
44902 case ISD::CONCAT_VECTORS: