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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc99150 /*223493*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::BITREVERSE),// ->223517
gen/lib/Target/AArch64/AArch64GenFastISel.inc 4271 case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc62848 /*137117*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::BITREVERSE),// ->137141
gen/lib/Target/ARM/ARMGenDAGISel.inc38441 /* 84709*/ /*SwitchOpcode*/ 62|128,1/*190*/, TARGET_VAL(ISD::BITREVERSE),// ->84903
gen/lib/Target/ARM/ARMGenFastISel.inc 2706 case ISD::BITREVERSE: return fastEmit_ISD_BITREVERSE_r(VT, RetVT, Op0, Op0IsKill);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc67950 /*131456*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::BITREVERSE),// ->131480
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc68772 /*145365*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::BITREVERSE),// ->145389
gen/lib/Target/PowerPC/PPCGenDAGISel.inc30365 /* 72790*/ /*SwitchOpcode*/ 28|128,107/*13724*/, TARGET_VAL(ISD::BITREVERSE),// ->86518
lib/CodeGen/CodeGenPrepare.cpp 7071 !TLI.isOperationLegalOrCustom(ISD::BITREVERSE,
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1540 case ISD::BITREVERSE: return visitBITREVERSE(N);
8046 return DAG.getNode(ISD::BITREVERSE, SDLoc(N), VT, N0);
8048 if (N0.getOpcode() == ISD::BITREVERSE)
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2678 case ISD::BITREVERSE:
4166 case ISD::BITREVERSE:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
402 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
1689 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2445 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2446 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 387 case ISD::BITREVERSE:
798 case ISD::BITREVERSE:
1093 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
1106 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
1115 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 73 case ISD::BITREVERSE:
885 case ISD::BITREVERSE:
2886 case ISD::BITREVERSE:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3211 case ISD::BITREVERSE: {
4323 case ISD::BITREVERSE:
4443 case ISD::BITREVERSE:
4616 case ISD::BITREVERSE:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6193 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 384 case ISD::BITREVERSE: return "bitreverse";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1531 case ISD::BITREVERSE: {
lib/CodeGen/TargetLoweringBase.cpp 681 setOperationAction(ISD::BITREVERSE, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 199 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
200 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
lib/Target/AMDGPU/SIISelLowering.cpp 353 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
453 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 266 setOperationAction(ISD::BITREVERSE, VT, Legal);
1067 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
5941 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
7771 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, cast);
lib/Target/Hexagon/HexagonISelLowering.cpp 1363 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1364 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
lib/Target/NVPTX/NVPTXISelLowering.cpp 417 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
418 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 157 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
158 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
lib/Target/X86/X86ISelLowering.cpp 1017 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Custom);
1084 setOperationAction(ISD::BITREVERSE, VT, Custom);
1088 setOperationAction(ISD::BITREVERSE, VT, Custom);
1168 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom);
1517 setOperationAction(ISD::BITREVERSE, MVT::v8i64, Custom);
1518 setOperationAction(ISD::BITREVERSE, MVT::v16i32, Custom);
1660 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custom);
27010 Res = DAG.getNode(ISD::BITREVERSE, DL, VecVT, Res);
27673 case ISD::BITREVERSE: return LowerBITREVERSE(Op, Subtarget, DAG);
lib/Target/X86/X86TargetTransformInfo.cpp 1901 { ISD::BITREVERSE, MVT::v8i64, 5 },
1902 { ISD::BITREVERSE, MVT::v16i32, 5 },
1903 { ISD::BITREVERSE, MVT::v32i16, 5 },
1904 { ISD::BITREVERSE, MVT::v64i8, 5 },
1927 { ISD::BITREVERSE, MVT::v8i64, 36 },
1928 { ISD::BITREVERSE, MVT::v16i32, 24 },
1945 { ISD::BITREVERSE, MVT::v4i64, 4 },
1946 { ISD::BITREVERSE, MVT::v8i32, 4 },
1947 { ISD::BITREVERSE, MVT::v16i16, 4 },
1948 { ISD::BITREVERSE, MVT::v32i8, 4 },
1949 { ISD::BITREVERSE, MVT::v2i64, 1 },
1950 { ISD::BITREVERSE, MVT::v4i32, 1 },
1951 { ISD::BITREVERSE, MVT::v8i16, 1 },
1952 { ISD::BITREVERSE, MVT::v16i8, 1 },
1953 { ISD::BITREVERSE, MVT::i64, 3 },
1954 { ISD::BITREVERSE, MVT::i32, 3 },
1955 { ISD::BITREVERSE, MVT::i16, 3 },
1956 { ISD::BITREVERSE, MVT::i8, 3 }
1959 { ISD::BITREVERSE, MVT::v4i64, 5 },
1960 { ISD::BITREVERSE, MVT::v8i32, 5 },
1961 { ISD::BITREVERSE, MVT::v16i16, 5 },
1962 { ISD::BITREVERSE, MVT::v32i8, 5 },
1996 { ISD::BITREVERSE, MVT::v4i64, 12 }, // 2 x 128-bit Op + extract/insert
1997 { ISD::BITREVERSE, MVT::v8i32, 12 }, // 2 x 128-bit Op + extract/insert
1998 { ISD::BITREVERSE, MVT::v16i16, 12 }, // 2 x 128-bit Op + extract/insert
1999 { ISD::BITREVERSE, MVT::v32i8, 12 }, // 2 x 128-bit Op + extract/insert
2051 { ISD::BITREVERSE, MVT::v2i64, 5 },
2052 { ISD::BITREVERSE, MVT::v4i32, 5 },
2053 { ISD::BITREVERSE, MVT::v8i16, 5 },
2054 { ISD::BITREVERSE, MVT::v16i8, 5 },
2072 { ISD::BITREVERSE, MVT::v2i64, 29 },
2073 { ISD::BITREVERSE, MVT::v4i32, 27 },
2074 { ISD::BITREVERSE, MVT::v8i16, 27 },
2075 { ISD::BITREVERSE, MVT::v16i8, 20 },
2123 { ISD::BITREVERSE, MVT::i64, 14 },
2130 { ISD::BITREVERSE, MVT::i32, 14 },
2131 { ISD::BITREVERSE, MVT::i16, 14 },
2132 { ISD::BITREVERSE, MVT::i8, 11 },
2153 ISD = ISD::BITREVERSE;