reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenDAGISel.inc

96969 /*219231*/  /*SwitchOpcode*/ 58|128,2/*314*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->219549

gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc

49721 /*106896*/  /*SwitchOpcode*/ 25|128,3/*409*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->107309

gen/lib/Target/AMDGPU/R600GenDAGISel.inc

 7543 /* 28949*/  /*SwitchOpcode*/ 113, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->29065

gen/lib/Target/AVR/AVRGenDAGISel.inc

 1237 /*  2140*/  /*SwitchOpcode*/ 34, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->2177

gen/lib/Target/Mips/MipsGenDAGISel.inc

23888 /* 44814*/  /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->44884

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

57524 /*122452*/  /*SwitchOpcode*/ 111|128,3/*495*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->122951

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

22251 /* 55180*/  /*SwitchOpcode*/ 79, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->55262

gen/lib/Target/RISCV/RISCVGenDAGISel.inc

 9523 /* 17622*/  /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->18099

gen/lib/Target/SystemZ/SystemZGenDAGISel.inc

20051 /* 37577*/  /*SwitchOpcode*/ 56|128,1/*184*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->37765

gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc

  607 /*   967*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
  641 /*  1027*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
  675 /*  1086*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
  709 /*  1146*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 1143 /*  1943*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 1176 /*  2006*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 1701 /*  2990*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 1732 /*  3050*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 2399 /*  4246*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 2428 /*  4298*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 2457 /*  4349*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 2486 /*  4401*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 2961 /*  5256*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 2987 /*  5304*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 3395 /*  6088*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 3423 /*  6143*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 3983 /*  7209*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 4009 /*  7261*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 4381 /*  7974*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 4402 /*  8014*/      OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),
 5579 /* 10186*/      /*SwitchOpcode*/ 88|128,1/*216*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->10406
 6868 /* 12700*/      /*SwitchOpcode*/ 105|128,2/*361*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->13065
14208 /* 27666*/  /*SwitchOpcode*/ 89|128,4/*601*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->28271

include/llvm/CodeGen/SelectionDAGNodes.h

 1415            N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||
 1472            N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3785   case ISD::ATOMIC_LOAD_XOR:

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  171   case ISD::ATOMIC_LOAD_XOR:
 1721   case ISD::ATOMIC_LOAD_XOR:

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  597   case ISD::ATOMIC_LOAD_XOR:
 6522           Opcode == ISD::ATOMIC_LOAD_XOR ||

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 4598   case AtomicRMWInst::Xor:  NT = ISD::ATOMIC_LOAD_XOR; break;

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

   92   case ISD::ATOMIC_LOAD_XOR:            return "AtomicLoadXor";

lib/CodeGen/TargetLoweringBase.cpp

  464     OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)

lib/Target/AMDGPU/SIISelLowering.cpp

  741   setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
 9981   case ISD::ATOMIC_LOAD_XOR:

lib/Target/ARM/ARMISelLowering.cpp

 1233     setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Expand);

lib/Target/Mips/Mips16ISelLowering.cpp

  137   setOperationAction(ISD::ATOMIC_LOAD_XOR,    MVT::i32,   Expand);

lib/Target/SystemZ/SystemZISelLowering.cpp

  226   setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Custom);
 4994   case ISD::ATOMIC_LOAD_XOR:

lib/Target/X86/X86ISelLowering.cpp

  471     setOperationAction(ISD::ATOMIC_LOAD_XOR, VT, Custom);
27116   case ISD::ATOMIC_LOAD_XOR:
27670   case ISD::ATOMIC_LOAD_XOR:
28426   case ISD::ATOMIC_LOAD_XOR: