reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
163 if (unsigned Reg = State.AllocateReg(RegList3)) { 192 if (unsigned Reg = State.AllocateReg(RegList4)) { 339 if (unsigned Reg = State.AllocateReg(RegList21)) { 582 if (unsigned Reg = State.AllocateReg(RegList17)) { 850 if (unsigned Reg = State.AllocateReg(RegList1)) { 860 if (unsigned Reg = State.AllocateReg(RegList2)) { 870 if (unsigned Reg = State.AllocateReg(RegList3)) { 892 if (unsigned Reg = State.AllocateReg(RegList4)) { 1152 if (unsigned Reg = State.AllocateReg(RegList13)) { 1173 if (unsigned Reg = State.AllocateReg(RegList14)) { 1186 if (unsigned Reg = State.AllocateReg(RegList15)) {gen/lib/Target/AMDGPU/AMDGPUGenCallingConv.inc
87 if (unsigned Reg = State.AllocateReg(RegList1)) { 168 if (unsigned Reg = State.AllocateReg(RegList1)) { 184 if (unsigned Reg = State.AllocateReg(RegList2)) { 231 if (unsigned Reg = State.AllocateReg(RegList1)) { 249 if (unsigned Reg = State.AllocateReg(RegList1)) { 261 if (unsigned Reg = State.AllocateReg(RegList2)) {gen/lib/Target/AMDGPU/R600GenCallingConv.inc
24 if (unsigned Reg = State.AllocateReg(RegList1)) {
gen/lib/Target/ARC/ARCGenCallingConv.inc37 if (unsigned Reg = State.AllocateReg(RegList1)) { 68 if (unsigned Reg = State.AllocateReg(RegList1)) {gen/lib/Target/ARM/ARMGenCallingConv.inc
157 if (unsigned Reg = State.AllocateReg(RegList3)) { 284 if (unsigned Reg = State.AllocateReg(RegList1)) { 294 if (unsigned Reg = State.AllocateReg(RegList2)) { 304 if (unsigned Reg = State.AllocateReg(RegList3)) { 391 if (unsigned Reg = State.AllocateReg(RegList1)) { 447 if (unsigned Reg = State.AllocateReg(RegList1)) { 457 if (unsigned Reg = State.AllocateReg(RegList2)) { 467 if (unsigned Reg = State.AllocateReg(RegList3)) { 488 if (unsigned Reg = State.AllocateReg(RegList4)) { 541 if (unsigned Reg = State.AllocateReg(RegList1)) { 551 if (unsigned Reg = State.AllocateReg(RegList2)) { 561 if (unsigned Reg = State.AllocateReg(RegList3)) { 683 if (unsigned Reg = State.AllocateReg(RegList1)) { 754 if (unsigned Reg = State.AllocateReg(RegList1)) { 764 if (unsigned Reg = State.AllocateReg(RegList2)) { 774 if (unsigned Reg = State.AllocateReg(RegList3)) { 856 if (unsigned Reg = State.AllocateReg(RegList1)) { 907 if (unsigned Reg = State.AllocateReg(RegList1)) { 917 if (unsigned Reg = State.AllocateReg(RegList2)) { 927 if (unsigned Reg = State.AllocateReg(RegList3)) {gen/lib/Target/AVR/AVRGenCallingConv.inc
31 if (unsigned Reg = State.AllocateReg(RegList1)) { 41 if (unsigned Reg = State.AllocateReg(RegList2)) { 78 if (unsigned Reg = State.AllocateReg(RegList1)) { 96 if (unsigned Reg = State.AllocateReg(RegList1)) { 106 if (unsigned Reg = State.AllocateReg(RegList2)) {gen/lib/Target/BPF/BPFGenCallingConv.inc
81 if (unsigned Reg = State.AllocateReg(RegList1)) {
gen/lib/Target/Hexagon/HexagonGenCallingConv.inc75 if (unsigned Reg = State.AllocateReg(RegList1)) { 96 if (unsigned Reg = State.AllocateReg(RegList2)) { 145 if (unsigned Reg = State.AllocateReg(RegList1)) { 159 if (unsigned Reg = State.AllocateReg(RegList2)) { 193 if (unsigned Reg = State.AllocateReg(RegList5)) { 207 if (unsigned Reg = State.AllocateReg(RegList6)) { 271 if (unsigned Reg = State.AllocateReg(RegList1)) { 283 if (unsigned Reg = State.AllocateReg(RegList2)) {gen/lib/Target/Lanai/LanaiGenCallingConv.inc
41 if (unsigned Reg = State.AllocateReg(RegList1)) { 77 if (unsigned Reg = State.AllocateReg(RegList1)) { 100 if (unsigned Reg = State.AllocateReg(RegList1)) {gen/lib/Target/MSP430/MSP430GenCallingConv.inc
54 if (unsigned Reg = State.AllocateReg(RegList1)) { 64 if (unsigned Reg = State.AllocateReg(RegList2)) {gen/lib/Target/Mips/MipsGenCallingConv.inc
99 if (unsigned Reg = State.AllocateReg(RegList1)) { 215 if (unsigned Reg = State.AllocateReg(RegList1)) { 225 if (unsigned Reg = State.AllocateReg(RegList2)) { 302 if (unsigned Reg = State.AllocateReg(RegList1)) { 313 if (unsigned Reg = State.AllocateReg(RegList2)) { 396 if (unsigned Reg = State.AllocateReg(RegList1)) { 409 if (unsigned Reg = State.AllocateReg(RegList2)) { 423 if (unsigned Reg = State.AllocateReg(RegList3)) { 486 if (unsigned Reg = State.AllocateReg(RegList1)) { 498 if (unsigned Reg = State.AllocateReg(RegList2)) { 510 if (unsigned Reg = State.AllocateReg(RegList3)) { 522 if (unsigned Reg = State.AllocateReg(RegList4)) { 644 if (unsigned Reg = State.AllocateReg(RegList1)) { 653 if (unsigned Reg = State.AllocateReg(RegList2)) { 669 if (unsigned Reg = State.AllocateReg(RegList1)) { 748 if (unsigned Reg = State.AllocateReg(RegList1)) { 758 if (unsigned Reg = State.AllocateReg(RegList2)) { 768 if (unsigned Reg = State.AllocateReg(RegList3)) { 799 if (unsigned Reg = State.AllocateReg(RegList1)) { 810 if (unsigned Reg = State.AllocateReg(RegList2)) { 821 if (unsigned Reg = State.AllocateReg(RegList3)) { 833 if (unsigned Reg = State.AllocateReg(RegList4)) {gen/lib/Target/PowerPC/PPCGenCallingConv.inc
52 if (unsigned Reg = State.AllocateReg(RegList1)) { 70 if (unsigned Reg = State.AllocateReg(RegList2)) { 82 if (unsigned Reg = State.AllocateReg(RegList3)) { 173 if (unsigned Reg = State.AllocateReg(RegList1)) { 192 if (unsigned Reg = State.AllocateReg(RegList2)) { 211 if (unsigned Reg = State.AllocateReg(RegList3)) { 362 if (unsigned Reg = State.AllocateReg(RegList1)) { 373 if (unsigned Reg = State.AllocateReg(RegList2)) { 421 if (unsigned Reg = State.AllocateReg(RegList1)) { 431 if (unsigned Reg = State.AllocateReg(RegList2)) { 441 if (unsigned Reg = State.AllocateReg(RegList3)) { 452 if (unsigned Reg = State.AllocateReg(RegList4)) { 464 if (unsigned Reg = State.AllocateReg(RegList5)) { 476 if (unsigned Reg = State.AllocateReg(RegList6)) { 495 if (unsigned Reg = State.AllocateReg(RegList7)) { 509 if (unsigned Reg = State.AllocateReg(RegList8)) { 527 if (unsigned Reg = State.AllocateReg(RegList9)) { 602 if (unsigned Reg = State.AllocateReg(RegList1)) { 612 if (unsigned Reg = State.AllocateReg(RegList2)) { 622 if (unsigned Reg = State.AllocateReg(RegList3)) { 632 if (unsigned Reg = State.AllocateReg(RegList4)) { 643 if (unsigned Reg = State.AllocateReg(RegList5)) { 657 if (unsigned Reg = State.AllocateReg(RegList6)) { 675 if (unsigned Reg = State.AllocateReg(RegList7)) {gen/lib/Target/Sparc/SparcGenCallingConv.inc
37 if (unsigned Reg = State.AllocateReg(RegList1)) { 98 if (unsigned Reg = State.AllocateReg(RegList1)) { 108 if (unsigned Reg = State.AllocateReg(RegList2)) { 118 if (unsigned Reg = State.AllocateReg(RegList3)) {gen/lib/Target/SystemZ/SystemZGenCallingConv.inc
65 if (unsigned Reg = State.AllocateReg(RegList1)) { 75 if (unsigned Reg = State.AllocateReg(RegList2)) { 85 if (unsigned Reg = State.AllocateReg(RegList3)) { 95 if (unsigned Reg = State.AllocateReg(RegList4)) { 112 if (unsigned Reg = State.AllocateReg(RegList5)) { 189 if (unsigned Reg = State.AllocateReg(RegList1)) { 199 if (unsigned Reg = State.AllocateReg(RegList2)) { 209 if (unsigned Reg = State.AllocateReg(RegList3)) { 219 if (unsigned Reg = State.AllocateReg(RegList4)) { 235 if (unsigned Reg = State.AllocateReg(RegList5)) {gen/lib/Target/X86/X86GenCallingConv.inc
176 if (unsigned Reg = State.AllocateReg(RegList1)) { 188 if (unsigned Reg = State.AllocateReg(RegList2)) { 200 if (unsigned Reg = State.AllocateReg(RegList3)) { 212 if (unsigned Reg = State.AllocateReg(RegList4)) { 234 if (unsigned Reg = State.AllocateReg(RegList6)) { 247 if (unsigned Reg = State.AllocateReg(RegList7)) { 260 if (unsigned Reg = State.AllocateReg(RegList8)) { 408 if (unsigned Reg = State.AllocateReg(RegList1)) { 440 if (unsigned Reg = State.AllocateReg(RegList1)) { 454 if (unsigned Reg = State.AllocateReg(RegList2)) { 592 if (unsigned Reg = State.AllocateReg(RegList1)) { 605 if (unsigned Reg = State.AllocateReg(RegList2)) { 652 if (unsigned Reg = State.AllocateReg(RegList1)) { 664 if (unsigned Reg = State.AllocateReg(RegList2)) { 676 if (unsigned Reg = State.AllocateReg(RegList3)) { 709 if (unsigned Reg = State.AllocateReg(RegList1)) { 738 if (unsigned Reg = State.AllocateReg(RegList1)) { 836 if (unsigned Reg = State.AllocateReg(RegList1)) { 882 if (unsigned Reg = State.AllocateReg(RegList2)) { 906 if (unsigned Reg = State.AllocateReg(RegList3)) { 923 if (unsigned Reg = State.AllocateReg(RegList4)) { 940 if (unsigned Reg = State.AllocateReg(RegList5)) { 1175 if (unsigned Reg = State.AllocateReg(RegList1)) { 1193 if (unsigned Reg = State.AllocateReg(RegList2)) { 1211 if (unsigned Reg = State.AllocateReg(RegList3)) { 1239 if (unsigned Reg = State.AllocateReg(RegList1)) { 1257 if (unsigned Reg = State.AllocateReg(RegList2)) { 1275 if (unsigned Reg = State.AllocateReg(RegList3)) { 1449 if (unsigned Reg = State.AllocateReg(RegList1)) { 1459 if (unsigned Reg = State.AllocateReg(RegList2)) { 1552 if (unsigned Reg = State.AllocateReg(RegList3)) { 1570 if (unsigned Reg = State.AllocateReg(RegList4)) { 1589 if (unsigned Reg = State.AllocateReg(RegList5)) { 1672 if (unsigned Reg = State.AllocateReg(RegList1)) { 1690 if (unsigned Reg = State.AllocateReg(RegList2)) { 1707 if (unsigned Reg = State.AllocateReg(RegList3)) { 1724 if (unsigned Reg = State.AllocateReg(RegList4)) { 1743 if (unsigned Reg = State.AllocateReg(RegList1)) { 1791 if (unsigned Reg = State.AllocateReg(RegList1)) { 1902 if (unsigned Reg = State.AllocateReg(RegList1)) { 1912 if (unsigned Reg = State.AllocateReg(RegList2)) { 1933 if (unsigned Reg = State.AllocateReg(RegList3)) { 1954 if (unsigned Reg = State.AllocateReg(RegList4)) { 1978 if (unsigned Reg = State.AllocateReg(RegList5)) { 1995 if (unsigned Reg = State.AllocateReg(RegList6)) { 2012 if (unsigned Reg = State.AllocateReg(RegList7)) { 2365 if (unsigned Reg = State.AllocateReg(RegList1)) { 2375 if (unsigned Reg = State.AllocateReg(RegList2)) { 2396 if (unsigned Reg = State.AllocateReg(RegList3)) { 2417 if (unsigned Reg = State.AllocateReg(RegList4)) { 2441 if (unsigned Reg = State.AllocateReg(RegList5)) { 2458 if (unsigned Reg = State.AllocateReg(RegList6)) { 2475 if (unsigned Reg = State.AllocateReg(RegList7)) { 2594 if (unsigned Reg = State.AllocateReg(RegList1)) { 2607 if (unsigned Reg = State.AllocateReg(RegList2)) { 2620 if (unsigned Reg = State.AllocateReg(RegList3)) { 2682 if (unsigned Reg = State.AllocateReg(RegList1)) { 2692 if (unsigned Reg = State.AllocateReg(RegList2)) { 2702 if (unsigned Reg = State.AllocateReg(RegList3)) { 2712 if (unsigned Reg = State.AllocateReg(RegList4)) { 2787 if (unsigned Reg = State.AllocateReg(RegList5)) { 2802 if (unsigned Reg = State.AllocateReg(RegList6)) { 2817 if (unsigned Reg = State.AllocateReg(RegList7)) { 2835 if (unsigned Reg = State.AllocateReg(RegList8)) { 2893 if (unsigned Reg = State.AllocateReg(RegList1)) { 2906 if (unsigned Reg = State.AllocateReg(RegList2)) { 2928 if (unsigned Reg = State.AllocateReg(RegList1)) { 2940 if (unsigned Reg = State.AllocateReg(RegList2)) { 2951 if (unsigned Reg = State.AllocateReg(RegList3)) { 2961 if (unsigned Reg = State.AllocateReg(RegList4)) { 2971 if (unsigned Reg = State.AllocateReg(RegList5)) { 3003 if (unsigned Reg = State.AllocateReg(RegList1)) { 3053 if (unsigned Reg = State.AllocateReg(RegList1)) { 3063 if (unsigned Reg = State.AllocateReg(RegList2)) { 3073 if (unsigned Reg = State.AllocateReg(RegList3)) { 3116 if (unsigned Reg = State.AllocateReg(RegList4)) { 3129 if (unsigned Reg = State.AllocateReg(RegList5)) { 3146 if (unsigned Reg = State.AllocateReg(RegList6)) { 3163 if (unsigned Reg = State.AllocateReg(RegList7)) { 3180 if (unsigned Reg = State.AllocateReg(RegList8)) { 3201 if (unsigned Reg = State.AllocateReg(RegList1)) { 3301 if (unsigned Reg = State.AllocateReg(RegList1)) { 3311 if (unsigned Reg = State.AllocateReg(RegList2)) { 3321 if (unsigned Reg = State.AllocateReg(RegList3)) { 3331 if (unsigned Reg = State.AllocateReg(RegList4)) { 3373 if (unsigned Reg = State.AllocateReg(RegList1)) { 3403 if (unsigned Reg = State.AllocateReg(RegList1)) { 3450 if (unsigned Reg = State.AllocateReg(RegList1)) { 3460 if (unsigned Reg = State.AllocateReg(RegList2)) { 3470 if (unsigned Reg = State.AllocateReg(RegList3)) { 3480 if (unsigned Reg = State.AllocateReg(RegList4)) { 3490 if (unsigned Reg = State.AllocateReg(RegList5)) { 3500 if (unsigned Reg = State.AllocateReg(RegList6)) { 3510 if (unsigned Reg = State.AllocateReg(RegList7)) { 3520 if (unsigned Reg = State.AllocateReg(RegList8)) { 3543 if (unsigned Reg = State.AllocateReg(RegList1)) { 3623 if (unsigned Reg = State.AllocateReg(RegList1)) { 3633 if (unsigned Reg = State.AllocateReg(RegList2)) { 3643 if (unsigned Reg = State.AllocateReg(RegList3)) { 3653 if (unsigned Reg = State.AllocateReg(RegList4)) { 3674 if (unsigned Reg = State.AllocateReg(RegList5)) { 3692 if (unsigned Reg = State.AllocateReg(RegList6)) { 3705 if (unsigned Reg = State.AllocateReg(RegList7)) { 3722 if (unsigned Reg = State.AllocateReg(RegList8)) { 3739 if (unsigned Reg = State.AllocateReg(RegList9)) { 3756 if (unsigned Reg = State.AllocateReg(RegList10)) { 3823 if (unsigned Reg = State.AllocateReg(RegList1)) { 3833 if (unsigned Reg = State.AllocateReg(RegList2)) { 3843 if (unsigned Reg = State.AllocateReg(RegList3)) { 3853 if (unsigned Reg = State.AllocateReg(RegList4)) { 3874 if (unsigned Reg = State.AllocateReg(RegList5)) { 3892 if (unsigned Reg = State.AllocateReg(RegList6)) { 3905 if (unsigned Reg = State.AllocateReg(RegList7)) { 3922 if (unsigned Reg = State.AllocateReg(RegList8)) { 3939 if (unsigned Reg = State.AllocateReg(RegList9)) { 3956 if (unsigned Reg = State.AllocateReg(RegList10)) {gen/lib/Target/XCore/XCoreGenCallingConv.inc
43 if (unsigned Reg = State.AllocateReg(RegList1)) { 67 if (unsigned Reg = State.AllocateReg(RegList1)) {lib/Target/ARM/ARMCallingConv.cpp
27 if (unsigned Reg = State.AllocateReg(RegList)) 42 if (unsigned Reg = State.AllocateReg(RegList)) 76 Reg = State.AllocateReg(GPRArgRegs);lib/Target/ARM/ARMISelLowering.cpp
2459 unsigned Reg = State->AllocateReg(GPRArgRegs); 2466 Reg = State->AllocateReg(GPRArgRegs); 2479 while (State->AllocateReg(GPRArgRegs)) 2496 State->AllocateReg(GPRArgRegs);lib/Target/AVR/AVRISelLowering.cpp
982 unsigned Reg = CCInfo.AllocateReg(
lib/Target/MSP430/MSP430ISelLowering.cpp514 unsigned Reg = State.AllocateReg(RegList); 522 unsigned Reg = State.AllocateReg(RegList);lib/Target/Mips/MipsISelLowering.cpp
2797 Reg = State.AllocateReg(FloatVectorIntRegs); 2805 Reg = State.AllocateReg(IntRegs); 2808 Reg = State.AllocateReg(IntRegs); 2812 Reg = State.AllocateReg(IntRegs); 2817 Reg = State.AllocateReg(IntRegs); 2819 Reg = State.AllocateReg(IntRegs); 2820 State.AllocateReg(IntRegs); 2825 Reg = State.AllocateReg(F32Regs); 2827 State.AllocateReg(IntRegs); 2829 Reg = State.AllocateReg(F64Regs); 2831 unsigned Reg2 = State.AllocateReg(IntRegs); 2833 State.AllocateReg(IntRegs); 2834 State.AllocateReg(IntRegs);lib/Target/PowerPC/PPCCallingConv.cpp
118 unsigned Reg = State.AllocateReg(HiRegList);
lib/Target/PowerPC/PPCISelLowering.cpp6746 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { 6766 if (unsigned Reg = State.AllocateReg(FPR)) 6775 State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32);lib/Target/RISCV/RISCVISelLowering.cpp
1415 if (Register Reg = State.AllocateReg(ArgGPRs)) { 1432 if (Register Reg = State.AllocateReg(ArgGPRs)) { 1513 State.AllocateReg(ArgGPRs); 1532 Register Reg = State.AllocateReg(ArgGPRs); 1540 if (!State.AllocateReg(ArgGPRs)) 1580 Reg = State.AllocateReg(ArgGPRs); 1819 if (unsigned Reg = State.AllocateReg(GPRList)) { 1831 if (unsigned Reg = State.AllocateReg(FPR32List)) { 1843 if (unsigned Reg = State.AllocateReg(FPR64List)) {lib/Target/Sparc/SparcISelLowering.cpp
62 if (unsigned Reg = State.AllocateReg(RegList)) { 73 if (unsigned Reg = State.AllocateReg(RegList)) 91 if (unsigned Reg = State.AllocateReg(RegList)) 97 if (unsigned Reg = State.AllocateReg(RegList))lib/Target/SystemZ/SystemZCallingConv.h
110 unsigned Reg = State.AllocateReg(SystemZ::ArgGPRs);
lib/Target/X86/X86CallingConv.cpp149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT)); 157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs()); 160 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { 211 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { 261 if (unsigned Reg = State.AllocateReg(RegList)) {