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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/FunctionLoweringInfo.h 224 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
246 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
269 LiveOutRegInfo[Reg].IsValid = false;
include/llvm/CodeGen/LiveIntervals.h 116 return *VirtRegIntervals[Reg.id()];
134 VirtRegIntervals[Reg.id()] = createInterval(Reg);
135 return *VirtRegIntervals[Reg.id()];
146 delete VirtRegIntervals[Reg];
147 VirtRegIntervals[Reg] = nullptr;
include/llvm/CodeGen/LiveRangeCalc.h 257 Map[MBB] = LiveOutPair(VNI, nullptr);
include/llvm/CodeGen/MachineRegisterInfo.h 112 return VRegInfo[RegNo.id()].second;
438 VReg2Name[Reg] = Name.str();
677 VRegInfo[Reg].first = RCOrRB;
764 RegAllocHints[VReg].first = Type;
765 RegAllocHints[VReg].second.clear();
766 RegAllocHints[VReg].second.push_back(PrefReg);
773 RegAllocHints[VReg].second.push_back(PrefReg);
783 assert (RegAllocHints[VReg].first == 0 &&
785 RegAllocHints[VReg].second.clear();
include/llvm/CodeGen/VirtRegMap.h 115 assert(Virt2PhysMap[virtReg.id()] != NO_PHYS_REG &&
117 Virt2PhysMap[virtReg.id()] = NO_PHYS_REG;
136 Virt2SplitMap[virtReg.id()] = SReg;
lib/CodeGen/LiveIntervals.cpp 111 delete VirtRegIntervals[Register::index2VirtReg(i)];
lib/CodeGen/LiveRangeCalc.cpp 233 Map[MBB] = LiveOutPair(I.Value, nullptr);
303 const LiveOutPair &LOB = Map[&B];
389 if (VNInfo *VNI = Map[Pred].first) {
444 Map[MF->getBlockNumbered(BN)] = LiveOutPair(TheVNI, nullptr);
509 IDomValue = Map[IDom->getBlock()];
514 Map[IDom->getBlock()].second = IDomValue.second =
519 LiveOutPair &Value = Map[Pred];
545 LiveOutPair &LOP = Map[MBB];
lib/CodeGen/LiveVariables.cpp 89 return VirtRegInfo[RegIdx];
657 for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
658 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
659 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
661 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
lib/CodeGen/MachineRegisterInfo.cpp 60 VRegInfo[Reg].first = RC;
65 VRegInfo[Reg].first = &RegBank;
166 VRegInfo[Reg].first = RegClass;
175 VRegInfo[Reg].first = VRegInfo[VReg].first;
175 VRegInfo[Reg].first = VRegInfo[VReg].first;
184 VRegToType[VReg] = Ty;
192 VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
206 if (!VRegInfo[Reg].second)
lib/CodeGen/RegAllocFast.cpp 249 int SS = StackSlotForVirtReg[VirtReg];
261 StackSlotForVirtReg[VirtReg] = FrameIdx;
1227 int SS = StackSlotForVirtReg[Reg];
lib/CodeGen/RegAllocGreedy.cpp 261 ExtraRegInfo[VirtReg.reg].Stage = Stage;
269 if (ExtraRegInfo[Reg].Stage == RS_New)
270 ExtraRegInfo[Reg].Stage = NewStage;
670 ExtraRegInfo[Old].Stage = RS_Assign;
672 ExtraRegInfo[New] = ExtraRegInfo[Old];
672 ExtraRegInfo[New] = ExtraRegInfo[Old];
693 if (ExtraRegInfo[Reg].Stage == RS_New)
694 ExtraRegInfo[Reg].Stage = RS_Assign;
696 if (ExtraRegInfo[Reg].Stage == RS_Split) {
700 } else if (ExtraRegInfo[Reg].Stage == RS_Memory) {
715 if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
888 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
925 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
1053 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
1055 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
1083 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
1086 ExtraRegInfo[Intf->reg].Cascade = Cascade;
3061 << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 397 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
431 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
lib/CodeGen/VirtRegMap.cpp 85 assert(Virt2PhysMap[virtReg.id()] == NO_PHYS_REG &&
90 Virt2PhysMap[virtReg.id()] = physReg;
121 assert(Virt2StackSlotMap[virtReg.id()] == NO_STACK_SLOT &&
124 return Virt2StackSlotMap[virtReg.id()] = createSpillSlot(RC);
129 assert(Virt2StackSlotMap[virtReg.id()] == NO_STACK_SLOT &&
134 Virt2StackSlotMap[virtReg.id()] = SS;
lib/Target/ARM/ARMLegalizerInfo.cpp 257 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
259 FCmp32Libcalls[CmpInst::FCMP_OGE] = {
261 FCmp32Libcalls[CmpInst::FCMP_OGT] = {
263 FCmp32Libcalls[CmpInst::FCMP_OLE] = {
265 FCmp32Libcalls[CmpInst::FCMP_OLT] = {
267 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
268 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
269 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
270 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
271 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
272 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
273 FCmp32Libcalls[CmpInst::FCMP_UNO] = {
275 FCmp32Libcalls[CmpInst::FCMP_ONE] = {
278 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
283 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
285 FCmp64Libcalls[CmpInst::FCMP_OGE] = {
287 FCmp64Libcalls[CmpInst::FCMP_OGT] = {
289 FCmp64Libcalls[CmpInst::FCMP_OLE] = {
291 FCmp64Libcalls[CmpInst::FCMP_OLT] = {
293 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
294 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
295 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
296 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
297 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
298 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
299 FCmp64Libcalls[CmpInst::FCMP_UNO] = {
301 FCmp64Libcalls[CmpInst::FCMP_ONE] = {
304 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
313 FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
314 FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
315 FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
316 FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
317 FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
318 FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
319 FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
320 FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
321 FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
322 FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
323 FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
324 FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
325 FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
327 FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
331 FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
332 FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
333 FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
334 FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
335 FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
336 FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
337 FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
338 FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
339 FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
340 FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
341 FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
342 FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
343 FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
345 FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
lib/Target/SystemZ/SystemZFrameLowering.cpp 55 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
tools/clang/tools/extra/clang-doc/BitcodeWriter.cpp 125 BlockIdNameMap[Init.first] = Init.second;
191 RecordIdNameMap[Init.first] = Init.second;
tools/clang/tools/extra/clang-tidy/abseil/DurationRewriter.cpp 50 InverseMap[DurationScale::Hours] =
52 InverseMap[DurationScale::Minutes] =
54 InverseMap[DurationScale::Seconds] =
56 InverseMap[DurationScale::Milliseconds] = std::make_pair(
58 InverseMap[DurationScale::Microseconds] = std::make_pair(
60 InverseMap[DurationScale::Nanoseconds] = std::make_pair(
utils/TableGen/PseudoLoweringEmitter.cpp 82 OperandMap[BaseIdx + i].Kind = OpData::Reg;
83 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
101 OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
104 OperandMap[BaseIdx + i].Kind = OpData::Imm;
105 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
176 if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
187 OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
226 switch (Expansion.OperandMap[MIOpNo + i].Kind) {
229 << Source.Operands[Expansion.OperandMap[MIOpNo].Data
236 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
239 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
utils/TableGen/RISCVCompressInstEmitter.cpp 195 OperandMap[i].Kind = OperandMap[TiedOpIdx].Kind;
195 OperandMap[i].Kind = OperandMap[TiedOpIdx].Kind;
196 OperandMap[i].Data = OperandMap[TiedOpIdx].Data;
196 OperandMap[i].Data = OperandMap[TiedOpIdx].Data;
209 OperandMap[i].Kind = OpData::Reg;
210 OperandMap[i].Data.Reg = DI->getDef();
226 OperandMap[i].Kind = OpData::Operand;
236 OperandMap[i].Kind = OpData::Imm;
237 OperandMap[i].Data.Imm = II->getValue();
314 SourceOperandMap[i].TiedOpIdx = it->getValue();
351 DestOperandMap[i].Data = DestOperandMap[TiedInstOpIdx].Data;
351 DestOperandMap[i].Data = DestOperandMap[TiedInstOpIdx].Data;
352 DestOperandMap[i].Kind = DestOperandMap[TiedInstOpIdx].Kind;
352 DestOperandMap[i].Kind = DestOperandMap[TiedInstOpIdx].Kind;
353 if (DestOperandMap[i].Kind == OpData::Operand)
356 LLVM_DEBUG(dbgs() << " " << DestOperandMap[i].Data.Operand
364 if (DestOperandMap[i].Kind != OpData::Operand)
379 DestOperandMap[i].Data.Operand = SourceOp->getValue();
380 SourceOperandMap[SourceOp->getValue()].Data.Operand = i;
641 if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
646 << std::to_string(SourceOperandMap[OpNo].TiedOpIdx)
652 switch (SourceOperandMap[OpNo].Kind) {
661 std::to_string(SourceOperandMap[OpNo].Data.Imm) + ") &&\n";
664 Record *Reg = SourceOperandMap[OpNo].Data.Reg;
678 switch (DestOperandMap[OpNo].Kind) {
680 unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
715 std::to_string(DestOperandMap[OpNo].Data.Imm) + "), STI, " +
719 std::to_string(DestOperandMap[OpNo].Data.Imm) + "));\n";
723 Record *Reg = DestOperandMap[OpNo].Data.Reg;