|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc40609 /* 77546*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
40616 /* 77560*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
40656 /* 77632*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
64127 /*123114*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
64141 /*123152*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
64153 /*123185*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
64167 /*123222*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
64190 /*123282*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
64202 /*123315*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
65306 /*125566*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
65335 /*125661*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
65362 /*125750*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
68151 /*131827*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
68173 /*131893*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
68193 /*131954*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
68224 /*132051*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
68246 /*132117*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
68266 /*132178*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69720 /*134900*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69738 /*134954*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69779 /*135056*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69869 /*135266*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69889 /*135326*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69908 /*135383*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69932 /*135449*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69952 /*135509*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
69971 /*135566*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70038 /*135707*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70051 /*135744*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70092 /*135835*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70109 /*135886*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70156 /*136001*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70173 /*136054*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70222 /*136180*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70238 /*136226*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70256 /*136280*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70369 /*136484*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70381 /*136513*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70390 /*136536*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70402 /*136564*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70414 /*136593*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70423 /*136616*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70435 /*136644*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70447 /*136673*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70456 /*136696*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70584 /*136975*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70606 /*137043*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70626 /*137106*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70763 /*137420*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70785 /*137488*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70805 /*137551*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70942 /*137865*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70964 /*137933*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
70984 /*137996*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71202 /*138399*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71215 /*138436*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71250 /*138511*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71263 /*138548*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71298 /*138623*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71311 /*138660*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71339 /*138723*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71352 /*138761*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
71365 /*138799*/ OPC_EmitInteger, MVT::i32, Hexagon::vsub_hi,
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 3183 { 0, 0, 0, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, },
lib/Target/Hexagon/HexagonBitSimplify.cpp 419 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
lib/Target/Hexagon/HexagonExpandCondsets.cpp 265 case Hexagon::vsub_hi:
lib/Target/Hexagon/HexagonFrameLowering.cpp 1750 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1797 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 1014 : Hexagon::vsub_hi;
1045 Hi, DAG.getTargetConstant(Hexagon::vsub_hi, dl, MVT::i32),
1408 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, Vec);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 775 SubIdx = Hexagon::vsub_hi;
887 V1 = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, VecV);
896 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi;
1394 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResTy, Pair);
lib/Target/Hexagon/HexagonInstrInfo.cpp 853 Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1066 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1083 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1093 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1126 BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1301 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1313 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
lib/Target/Hexagon/HexagonRegisterInfo.cpp 313 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };