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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 4464 Inst.addOperand(MCOperand::createReg(ARM::ZR));
9192 case ARM::ZR: OpKind = MCK_GPRwithZRnosp; break;
gen/lib/Target/ARM/ARMGenAsmWriter.inc12569 MI->getOperand(1).getReg() == ARM::ZR &&
12570 MI->getOperand(2).getReg() == ARM::ZR &&
12593 MI->getOperand(1).getReg() == ARM::ZR &&
12594 MI->getOperand(2).getReg() == ARM::ZR &&
gen/lib/Target/ARM/ARMGenDAGISel.inc11245 /* 23893*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11258 /* 23923*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11271 /* 23953*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11284 /* 23983*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11297 /* 24013*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11310 /* 24043*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11323 /* 24073*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11336 /* 24103*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11352 /* 24139*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11365 /* 24169*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11378 /* 24199*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11391 /* 24229*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11404 /* 24259*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11417 /* 24289*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11430 /* 24319*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11443 /* 24349*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11459 /* 24385*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11472 /* 24415*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11485 /* 24445*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11498 /* 24475*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11511 /* 24505*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11524 /* 24535*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11537 /* 24565*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11550 /* 24595*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11566 /* 24631*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11579 /* 24661*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11592 /* 24691*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11605 /* 24721*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11618 /* 24751*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11631 /* 24781*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11647 /* 24817*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11660 /* 24847*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11673 /* 24877*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11686 /* 24907*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11699 /* 24937*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
11712 /* 24967*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12220 /* 26099*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12234 /* 26130*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12248 /* 26161*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12262 /* 26192*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12276 /* 26223*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12290 /* 26254*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12304 /* 26285*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12318 /* 26316*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12335 /* 26353*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12349 /* 26384*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12363 /* 26415*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12377 /* 26446*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12391 /* 26477*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12405 /* 26508*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12419 /* 26539*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12433 /* 26570*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12450 /* 26607*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12464 /* 26638*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12478 /* 26669*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12492 /* 26700*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12506 /* 26731*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12520 /* 26762*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12534 /* 26793*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12548 /* 26824*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12565 /* 26861*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12579 /* 26892*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12593 /* 26923*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12607 /* 26954*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12621 /* 26985*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12635 /* 27016*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12652 /* 27053*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12666 /* 27084*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12680 /* 27115*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12694 /* 27146*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12708 /* 27177*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
12722 /* 27208*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
37257 /* 82013*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
37267 /* 82040*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
37509 /* 82614*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
37519 /* 82641*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
46807 /*103815*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
46818 /*103844*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
46829 /*103873*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49780 /*110760*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49802 /*110813*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49824 /*110866*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49846 /*110919*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49868 /*110972*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49882 /*111005*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49895 /*111037*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49908 /*111069*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49932 /*111127*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49954 /*111180*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49976 /*111233*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
49998 /*111286*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50020 /*111339*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50034 /*111372*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50047 /*111404*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50060 /*111436*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50084 /*111494*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50106 /*111547*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50128 /*111600*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50150 /*111653*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50172 /*111706*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50186 /*111739*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50199 /*111771*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50212 /*111803*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50236 /*111861*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50258 /*111914*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50280 /*111967*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50302 /*112020*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50324 /*112073*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50338 /*112106*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50362 /*112164*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50384 /*112217*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50406 /*112270*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50428 /*112323*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50450 /*112376*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
50464 /*112409*/ OPC_EmitRegister, MVT::i32, ARM::ZR,
gen/lib/Target/ARM/ARMGenGlobalISel.inc24543 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
24581 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
24619 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
27423 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
27501 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
27793 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
27871 GIR_AddRegister, /*InsnID*/0, ARM::ZR, /*AddRegisterRegFlags*/0,
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 1495 { ARM::ZR },
1627 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1667 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
3032 { 15U, ARM::ZR },
3084 { 15U, ARM::ZR },
3124 { ARM::ZR, 15U },
3177 { ARM::ZR, 15U },
5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
6015 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR };
lib/Target/ARM/ARMBaseRegisterInfo.cpp 216 markSuperRegs(Reserved, ARM::ZR);
lib/Target/ARM/ARMISelLowering.cpp 4962 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 1186 Inst.addOperand(MCOperand::createReg(ARM::ZR));