|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 4398 Inst.addOperand(MCOperand::createReg(ARM::SP));
9091 case ARM::SP: OpKind = MCK_GPRsp; break;
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5297 static const MCPhysReg ImplicitList2[] = { ARM::SP, 0 };
5299 static const MCPhysReg ImplicitList4[] = { ARM::R7, ARM::LR, ARM::SP, 0 };
5304 static const MCPhysReg ImplicitList9[] = { ARM::R4, ARM::SP, 0 };
5311 static const MCPhysReg ImplicitList16[] = { ARM::R11, ARM::LR, ARM::SP, 0 };
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 1492 { ARM::SP },
1607 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1617 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1627 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1647 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1707 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1737 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1877 ARM::SP,
3030 { 13U, ARM::SP },
3082 { 13U, ARM::SP },
3123 { ARM::SP, 13U },
3176 { ARM::SP, 13U },
5939 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5941 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC };
5959 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
5995 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5997 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP };
16033 static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
lib/Target/ARM/ARMAsmPrinter.cpp 1085 SrcReg = DstReg = ARM::SP;
1094 assert(DstReg == ARM::SP &&
1116 assert(SrcReg == ARM::SP &&
1148 assert(MI->getOperand(2).getReg() == ARM::SP &&
1161 if (SrcReg == ARM::SP) {
1205 if (DstReg == FramePtr && FramePtr != ARM::SP)
1208 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1209 else if (DstReg == ARM::SP) {
1219 } else if (DstReg == ARM::SP) {
1973 .addReg(ARM::SP)
2044 .addReg(ARM::SP)
2108 .addReg(ARM::SP)
lib/Target/ARM/ARMBaseInstrInfo.cpp 1986 if (!MI.isCall() && MI.definesRegister(ARM::SP))
2420 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2421 MI->getOperand(1).getReg() == ARM::SP)) &&
lib/Target/ARM/ARMBaseRegisterInfo.cpp 193 markSuperRegs(Reserved, ARM::SP);
453 return ARM::SP;
620 if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
724 NumBits = (BaseReg == ARM::SP ? 8 : 5);
771 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
lib/Target/ARM/ARMBaseRegisterInfo.h 49 case LR: case SP: case PC:
lib/Target/ARM/ARMCallLowering.cpp 103 MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
lib/Target/ARM/ARMExpandPseudoInsts.cpp 1941 .addReg(ARM::SP, RegState::Define)
1942 .addReg(ARM::SP)
lib/Target/ARM/ARMFastISel.cpp 2023 Addr.Base.Reg = ARM::SP;
lib/Target/ARM/ARMFrameLowering.cpp 160 MI.getOperand(1).getReg() == ARM::SP)
185 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
185 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
556 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
557 .addReg(ARM::SP, RegState::Kill)
598 dl, TII, FramePtr, ARM::SP,
723 emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
734 .addReg(ARM::SP, RegState::Kill)
738 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
754 .addReg(ARM::SP)
759 .addReg(ARM::SP)
821 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
835 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
842 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
847 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
899 FrameReg = ARM::SP;
1024 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1025 .addReg(ARM::SP)
1031 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)
1033 .addReg(ARM::SP)
1120 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1121 .addReg(ARM::SP)
1139 .addReg(ARM::SP, RegState::Define)
1140 .addReg(ARM::SP);
1210 .addReg(ARM::SP)
1228 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1534 if (RegClass && !RegClass->contains(ARM::SP))
2358 .addReg(ARM::SP, RegState::Define)
2359 .addReg(ARM::SP)
2383 .addReg(ARM::SP)
2387 .addReg(ARM::SP)
2401 .addReg(ARM::SP)
2500 .addReg(ARM::SP, RegState::Define)
2501 .addReg(ARM::SP)
2539 .addReg(ARM::SP, RegState::Define)
2540 .addReg(ARM::SP)
2546 .addReg(ARM::SP, RegState::Define)
2547 .addReg(ARM::SP)
2563 .addReg(ARM::SP, RegState::Define)
2564 .addReg(ARM::SP)
2587 .addReg(ARM::SP, RegState::Define)
2588 .addReg(ARM::SP)
lib/Target/ARM/ARMISelDAGToDAG.cpp 2947 cast<RegisterSDNode>(Ptr.getOperand(1))->getReg() == ARM::SP &&
2950 CurDAG->getRegister(ARM::SP, MVT::i32),
lib/Target/ARM/ARMISelLowering.cpp 1427 setStackPointerRegisterToSaveRestore(ARM::SP);
2037 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2123 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
5573 .Case("sp", ARM::SP)
10318 BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
10319 .addReg(ARM::SP, RegState::Kill)
16072 SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
16078 Chain = DAG.getCopyToReg(Chain, DL, ARM::SP, SP);
16093 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 644 assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
701 (isThumb1 && Base == ARM::SP) ? ARM::tADDrSPi :
709 (isThumb1 && Offset < 8 && Base != ARM::SP) ? ARM::tSUBi3 :
988 if (getLoadStoreBaseOp(MI).getReg() == ARM::SP &&
1030 if (PReg == ARM::SP || PReg == ARM::PC)
1056 if (Reg == ARM::SP || Reg == ARM::PC)
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 120 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
179 FPReg = ARM::SP;
1673 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
3900 .Case("r13", ARM::SP)
4257 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
4257 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
6440 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
6440 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
6441 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
6442 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
6442 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
6467 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
6531 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
6608 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
6739 (PairedReg == ARM::SP && !hasV8Ops()))
7191 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7210 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
7415 if (RmReg == ARM::SP && !hasV8Ops())
7718 if (Inst.getOperand(0).getReg() == ARM::SP &&
7719 Inst.getOperand(1).getReg() != ARM::SP)
8364 Inst.getOperand(0).getReg() != ARM::SP) {
9928 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9929 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9939 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
9940 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
10233 if (Inst.getOperand(0).getReg() == ARM::SP &&
10234 Inst.getOperand(1).getReg() == ARM::SP)
10238 (Inst.getOperand(0).getReg() == ARM::SP ||
10239 Inst.getOperand(1).getReg() == ARM::SP))
10259 if (Inst.getOperand(0).isReg() && Inst.getOperand(0).getReg() == ARM::SP &&
10284 if ((Reg == ARM::SP) && !hasV8Ops())
11082 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
11398 if (UC.getFPReg() != ARM::SP)
11405 if (SPReg == ARM::SP || SPReg == ARM::PC)
11841 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 602 if (MI.getOperand(0).getReg() == ARM::SP &&
603 MI.getOperand(1).getReg() != ARM::SP)
1117 ARM::R12, ARM::SP, ARM::LR, ARM::PC
3644 Inst.addOperand(MCOperand::createReg(ARM::SP));
3717 Inst.addOperand(MCOperand::createReg(ARM::SP));
4366 Inst.addOperand(MCOperand::createReg(ARM::SP));
4367 Inst.addOperand(MCOperand::createReg(ARM::SP));
4383 Inst.addOperand(MCOperand::createReg(ARM::SP));
4389 Inst.addOperand(MCOperand::createReg(ARM::SP));
4390 Inst.addOperand(MCOperand::createReg(ARM::SP));
4506 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 1108 unsigned CFARegister = ARM::SP;
1158 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp 143 assert((Reg != ARM::SP && Reg != ARM::PC) &&
1245 FPReg = ARM::SP;
1410 assert((NewSPReg == ARM::SP || NewSPReg == FPReg) &&
1416 if (NewSPReg == ARM::SP)
1423 assert((Reg != ARM::SP && Reg != ARM::PC) &&
1425 assert(FPReg == ARM::SP && "current FP must be SP");
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 149 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
163 if (MI->getOperand(2).getReg() == ARM::SP &&
178 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
192 if (MI->getOperand(2).getReg() == ARM::SP &&
207 if (MI->getOperand(0).getReg() == ARM::SP) {
220 if (MI->getOperand(0).getReg() == ARM::SP) {
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 1382 assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 89 if (MI.getOperand(OI).getReg() == ARM::SP ||
116 case ARM::SP:
202 unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
lib/Target/ARM/Thumb1FrameLowering.cpp 90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill)
97 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
97 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
107 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
107 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
303 .addReg(ARM::SP)
413 .addReg(ARM::SP, RegState::Kill)
428 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
441 .addReg(ARM::SP)
519 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
523 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
692 GPRsNoLRSP.reset(ARM::SP);
723 .addReg(ARM::SP)
lib/Target/ARM/Thumb2ITBlockPass.cpp 91 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
lib/Target/ARM/Thumb2InstrInfo.cpp 249 if (DestReg != ARM::SP && DestReg != BaseReg &&
296 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
296 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
302 BaseReg = ARM::SP;
307 if (BaseReg == ARM::SP) {
309 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
334 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
334 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
lib/Target/ARM/Thumb2SizeReduction.cpp 390 if (Reg == ARM::SP) {
423 if (MI->getOperand(1).getReg() == ARM::SP) {
528 if (BaseReg != ARM::SP)
541 if (BaseReg == ARM::SP &&
629 if (MI->getOperand(1).getReg() != ARM::SP) {
lib/Target/ARM/ThumbRegisterInfo.cpp 143 if (DestReg == ARM::SP)
144 assert(BaseReg == ARM::SP && "Unexpected!");
175 if (DestReg == ARM::SP || isSub)
219 if (DestReg == ARM::SP) {
220 if (BaseReg == ARM::SP) {
232 if (BaseReg == ARM::SP) {
297 unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
387 unsigned NumBits = (FrameReg == ARM::SP) ? 8 : 5;
406 if (NewOpc != Opcode && FrameReg != ARM::SP)
476 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
516 if (FrameReg == ARM::SP || STI.genExecuteOnly())
540 if (FrameReg == ARM::SP || STI.genExecuteOnly())