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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 9092 case ARM::LR: OpKind = MCK_GPRlr; break;
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5298 static const MCPhysReg ImplicitList3[] = { ARM::LR, 0 };
5299 static const MCPhysReg ImplicitList4[] = { ARM::R7, ARM::LR, ARM::SP, 0 };
5300 static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5301 static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5302 static const MCPhysReg ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5310 static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5311 static const MCPhysReg ImplicitList16[] = { ARM::R11, ARM::LR, ARM::SP, 0 };
gen/lib/Target/ARM/ARMGenMCPseudoLowering.inc 357 TmpInst.addOperand(MCOperand::createReg(ARM::LR));
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 1490 { ARM::LR },
1607 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1617 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1627 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1647 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1657 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
1667 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
1677 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1707 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1727 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1737 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1747 ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1777 ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1867 ARM::LR,
3031 { 14U, ARM::LR },
3083 { 14U, ARM::LR },
3121 { ARM::LR, 14U },
3174 { ARM::LR, 14U },
5939 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5941 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC };
5959 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
5995 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5997 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP };
6015 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR };
6033 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
6035 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
16003 static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16005 static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16007 static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16009 static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16011 static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
16013 static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16017 static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16021 static const MCPhysReg CSR_Win_AAPCS_CFGuard_Check_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16023 static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16025 static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16027 static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 };
16031 static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 };
16033 static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 };
16035 static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
lib/Target/ARM/ARMAsmPrinter.cpp 1306 .addReg(ARM::LR)
1352 .addReg(ARM::LR)
1372 .addReg(ARM::LR)
lib/Target/ARM/ARMBaseInstrInfo.cpp 4754 if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) &&
lib/Target/ARM/ARMBaseRegisterInfo.cpp 58 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
lib/Target/ARM/ARMBaseRegisterInfo.h 49 case LR: case SP: case PC:
lib/Target/ARM/ARMConstantIslandPass.cpp 1756 MI->getOperand(2).getReg() == ARM::LR &&
lib/Target/ARM/ARMExpandPseudoInsts.cpp 1577 .addReg(ARM::LR)
1928 assert(Reg == ARM::LR && "expect LR register!");
lib/Target/ARM/ARMFrameLowering.cpp 437 case ARM::LR:
644 case ARM::LR:
1088 if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
1136 Regs[0] = ARM::LR;
1676 SavedRegs.set(ARM::LR);
1682 SavedRegs.set(ARM::LR);
1729 if (Reg == ARM::LR)
1737 case ARM::LR:
1760 case ARM::LR:
1880 SavedRegs.set(ARM::LR);
1883 auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR);
1988 !(MF.getRegInfo().isLiveIn(ARM::LR) &&
1990 if (SavedRegs.test(ARM::LR)) {
1995 AvailableRegs.push_back(ARM::LR);
2014 if (Reg != ARM::LR && !MRI.isPhysRegUsed(Reg))
2017 if (Reg == ARM::LR)
2031 SavedRegs.set(ARM::LR);
2034 LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR);
2039 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) &&
2039 if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) &&
2058 (Reg == ARM::LR && !ExpensiveLRRestore)) {
2063 !(Reg == ARM::LR && AFI->isThumb1OnlyFunction()))
2127 SavedRegs.set(ARM::LR);
2130 AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
2497 .addReg(ARM::LR);
2503 .addReg(ARM::LR);
2513 nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
2533 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2538 .addReg(ARM::LR, RegState::Define)
2549 .addReg(ARM::LR);
lib/Target/ARM/ARMISelLowering.cpp 3602 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5546 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 1944 if (MO.getReg() != ARM::LR)
1959 if (Info.getReg() == ARM::LR) {
1978 if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR))
lib/Target/ARM/ARMLowOverheadLoops.cpp 151 MI->getOperand(0).getReg() == ARM::LR &&
160 MachineInstr *PredLRDef = SearchForDef(Start, MBB->rend(), ARM::LR);
164 MachineInstr *SuccLRDef = SearchForDef(Start, MBB->end(), ARM::LR);
190 if (Start->getOperand(0).getReg() == ARM::LR)
200 if (LiveRegs.contains(ARM::LR))
205 if (!SearchForUse(Start, MBB->end(), ARM::LR))
295 MO.getReg() == ARM::LR) {
397 MIB.addDef(ARM::LR);
422 MIB.addReg(ARM::LR);
454 MIB.addDef(ARM::LR);
472 MIB.addDef(ARM::LR);
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 3901 .Case("r14", ARM::LR)
4257 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
4258 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
7137 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
7192 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
7673 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
9934 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 1117 ARM::R12, ARM::SP, ARM::LR, ARM::PC
1124 ARM::R12, 0, ARM::LR, ARM::APSR
5966 Inst.addOperand(MCOperand::createReg(ARM::LR));
5967 Inst.addOperand(MCOperand::createReg(ARM::LR));
5979 Inst.addOperand(MCOperand::createReg(ARM::LR));
6005 Inst.addOperand(MCOperand::createReg(ARM::LR));
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 1169 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 110 case ARM::LR:
185 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
lib/Target/ARM/Thumb1FrameLowering.cpp 223 case ARM::LR:
288 case ARM::LR:
464 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
574 if (CSI.getReg() == ARM::LR)
691 GPRsNoLRSP.reset(ARM::LR);
728 .addReg(ARM::LR, RegState::Define)
781 .addReg(ARM::LR, RegState::Define)
829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
831 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
853 for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
874 static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
955 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
957 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
1030 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
1033 if (Reg == ARM::LR) {
lib/Target/ARM/Thumb2SizeReduction.cpp 388 if (isLROk && Reg == ARM::LR)