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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10224 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, },
10244 { 14 /* add */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, },
10265 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_4095Neg1_2__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095Neg }, },
10267 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_4095Neg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095Neg }, },
10268 { 18 /* addw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__T2SOImmNeg1_3__CondCode2_0, AMFBS_IsThumb2_UseNegativeImmediates, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_T2SOImmNeg }, },
11348 { 1600 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_1__Imm0_40951_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_Imm0_4095 }, },
11361 { 1600 /* sub */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
11381 { 1609 /* subw */, ARM::t2SUBri12, Convert__Reg1_1__Reg1_2__Imm0_40951_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_Imm0_4095 }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 5290 /* 10744*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2SUBri12), 0,
33293 /* 73271*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::t2SUBri12), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 6754 return fastEmitInst_ri(ARM::t2SUBri12, &ARM::GPRnopcRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 3616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SUBri12,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 6469 case ARM::t2SUBri12: {
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 7715 case ARM::t2SUBri12:
9761 case ARM::t2SUBri12:
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 599 case ARM::t2SUBri12:
lib/Target/ARM/Thumb2InstrInfo.cpp 339 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
521 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;