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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc14126 { 3390 /* vrev64 */, ARM::VREV64q32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc39371 /* 86569*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
39461 /* 86746*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
39536 /* 86886*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
39626 /* 87063*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
39854 /* 87504*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
39956 /* 87697*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
40367 /* 88498*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
40469 /* 88691*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
53081 /*118604*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
53109 /*118670*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q32), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 535 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
577 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1098 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1118 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1205 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1225 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1419 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1439 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1480 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
1500 return fastEmitInst_r(ARM::VREV64q32, &ARM::QPRRegClass, Op0, Op0IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 8883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8963 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
8979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9927 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
9991 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
10007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q32,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 9707 case ARM::VREV64q32: