reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
14124   { 3390 /* vrev64 */, ARM::VREV64q16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc
23070 /* 49631*/            OPC_EmitNode1, TARGET_VAL(ARM::VREV64q16), 0,
29740 /* 65471*/          OPC_EmitNode1, TARGET_VAL(ARM::VREV64q16), 0,
39401 /* 86628*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
39491 /* 86805*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
39701 /* 87203*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
39791 /* 87380*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
40019 /* 87821*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
40121 /* 88014*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
40397 /* 88557*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
40499 /* 88750*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
53061 /*118557*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
53129 /*118717*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64q16), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc
  514     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
  556     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
  991     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
 1011     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
 1195     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
 1215     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
 1312     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
 1332     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
 1470     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
 1490     return fastEmitInst_r(ARM::VREV64q16, &ARM::QPRRegClass, Op0, Op0IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc
 8915       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
 8931       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
 8995       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
 9011       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10791       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10807       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10871       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
10887       GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64q16,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc
 9706     case ARM::VREV64q16: