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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc14127 { 3390 /* vrev64 */, ARM::VREV64d32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc38745 /* 85407*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
38790 /* 85491*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
38823 /* 85553*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
38843 /* 85588*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
38906 /* 85706*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
38921 /* 85734*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
39276 /* 86401*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
39321 /* 86485*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
53032 /*118489*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
53100 /*118649*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d32), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 523 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
565 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
764 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
778 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1029 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1050 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1150 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1164 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1350 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
1371 return fastEmitInst_r(ARM::VREV64d32, &ARM::DPRRegClass, Op0, Op0IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 8223 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8633 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
8649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d32,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 9704 case ARM::VREV64d32: