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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc14125 { 3390 /* vrev64 */, ARM::VREV64d16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc38760 /* 85435*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
38805 /* 85519*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
38989 /* 85859*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
39009 /* 85894*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
39072 /* 86012*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
39087 /* 86040*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
39291 /* 86429*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
39336 /* 86513*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
53024 /*118470*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
53148 /*118762*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VREV64d16), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 502 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
544 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
757 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
771 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
922 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
943 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1143 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1157 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1243 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
1264 return fastEmitInst_r(ARM::VREV64d16, &ARM::DPRRegClass, Op0, Op0IsKill);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 8255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
8351 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9661 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
9677 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VREV64d16,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 9703 case ARM::VREV64d16: