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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc12616 { 2348 /* vld1 */, ARM::VLD1LNd32, Convert__Reg1_3__Reg1_8__Imm1_9__Tie0_1_1__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK__123_, MCK_DPR, MCK__91_, MCK_Imm, MCK__93_, MCK__125_, MCK_GPR, MCK_Imm }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc28476 /* 61742*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28499 /* 61808*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28522 /* 61874*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28545 /* 61940*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28568 /* 62006*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28591 /* 62072*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28614 /* 62138*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28642 /* 62222*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28670 /* 62306*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28698 /* 62390*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28726 /* 62474*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28754 /* 62558*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28782 /* 62642*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28809 /* 62723*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28836 /* 62804*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28863 /* 62885*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28890 /* 62966*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
28917 /* 63047*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
29034 /* 63404*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
29066 /* 63503*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
29098 /* 63602*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
29130 /* 63701*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
29162 /* 63800*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
29194 /* 63899*/ OPC_EmitNode1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
45856 /*101620*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
46110 /*102207*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::VLD1LNd32), 0|OPFL_Chain|OPFL_MemRefs,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 9144 case ARM::VLD1LNd32: {
lib/Target/ARM/ARMBaseInstrInfo.cpp 4220 case ARM::VLD1LNd32:
5165 case ARM::VLD1LNd32:
lib/Target/ARM/ARMExpandPseudoInsts.cpp 155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 8054 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;