reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
11847   { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_QPR, MCK_QPR, MCK_QPR }, },
11849   { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_QPR, MCK_QPR, MCK_QPR }, },
11851   { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11853   { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_QPR, MCK_QPR, MCK_QPR }, },
11855   { 2106 /* vbsl */, ARM::VBSLq, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_QPR, MCK_QPR, MCK_QPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc
 1245 /*  2642*/                  OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 1253 /*  2663*/                  OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2015 /*  4117*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2042 /*  4169*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2066 /*  4215*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2094 /*  4268*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2117 /*  4313*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2145 /*  4366*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2169 /*  4412*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2203 /*  4475*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2215 /*  4501*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2245 /*  4556*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2257 /*  4582*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2293 /*  4647*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2305 /*  4673*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2336 /*  4729*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2348 /*  4755*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2383 /*  4820*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2410 /*  4872*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2434 /*  4918*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2462 /*  4971*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2485 /*  5016*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2513 /*  5069*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2537 /*  5115*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2571 /*  5178*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2583 /*  5204*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2613 /*  5259*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2625 /*  5285*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2661 /*  5350*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2673 /*  5376*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2704 /*  5432*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
 2716 /*  5458*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
18631 /* 39869*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
18644 /* 39898*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
18657 /* 39927*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
18670 /* 39956*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
18696 /* 40014*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
52436 /*116958*/      OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLq), 0,
gen/lib/Target/ARM/ARMGenGlobalISel.inc
22724         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22748         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22772         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22796         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
22820         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLq,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc
10823     case ARM::VBSLq: