reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
11848   { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_1__Tie0_1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK_DPR, MCK_DPR, MCK_DPR }, },
11850   { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_DPR, MCK_DPR, MCK_DPR }, },
11852   { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11854   { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_DPR, MCK_DPR, MCK_DPR }, },
11856   { 2106 /* vbsl */, ARM::VBSLd, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_DPR, MCK_DPR, MCK_DPR }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc
 1223 /*  2592*/                  OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1231 /*  2613*/                  OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1278 /*  2710*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1306 /*  2763*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1330 /*  2809*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1358 /*  2862*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1381 /*  2907*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1409 /*  2960*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1433 /*  3006*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1467 /*  3069*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1479 /*  3095*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1509 /*  3150*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1521 /*  3176*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1557 /*  3241*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1569 /*  3267*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1600 /*  3323*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1612 /*  3349*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1647 /*  3414*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1674 /*  3466*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1698 /*  3512*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1726 /*  3565*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1749 /*  3610*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1777 /*  3663*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1801 /*  3709*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1835 /*  3772*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1847 /*  3798*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1877 /*  3853*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1889 /*  3879*/              OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1925 /*  3944*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1937 /*  3970*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1968 /*  4026*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
 1980 /*  4052*/            OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
18579 /* 39753*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
18592 /* 39782*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
18605 /* 39811*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
18618 /* 39840*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
18683 /* 39985*/        OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
52428 /*116937*/      OPC_MorphNodeTo1, TARGET_VAL(ARM::VBSLd), 0,
gen/lib/Target/ARM/ARMGenGlobalISel.inc
22604         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22628         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22652         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22676         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
22700         GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VBSLd,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc
10822     case ARM::VBSLd: