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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 6327 case AMDGPU::SCC: OpKind = MCK_SCC_CLASS; break;
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc79511 if (Reg != AMDGPU::SCC)
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 650 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
683 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
1413 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
15573 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
15613 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
15678 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
15718 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
15783 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
15823 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
19559 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
19604 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
19649 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
19694 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
19744 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
19755 GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc15329 static const MCPhysReg ImplicitList1[] = { AMDGPU::SCC, 0 };
15334 static const MCPhysReg ImplicitList6[] = { AMDGPU::EXEC, AMDGPU::SCC, 0 };
15336 static const MCPhysReg ImplicitList8[] = { AMDGPU::M0, AMDGPU::EXEC, AMDGPU::SCC, 0 };
15339 static const MCPhysReg ImplicitList11[] = { AMDGPU::EXEC, AMDGPU::VCC, AMDGPU::SCC, 0 };
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc 9313 { AMDGPU::SCC },
10005 AMDGPU::SCC,
12171 { AMDGPU::SCC, 0U },
12882 { AMDGPU::SCC, 0U },
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 712 case AMDGPU::SCC:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2051 unsigned CondReg = UseSCCBr ? (unsigned)AMDGPU::SCC : TRI->getVCC();
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 74 return Reg == AMDGPU::SCC;
123 if (SrcReg == AMDGPU::SCC) {
423 .addReg(AMDGPU::SCC);
734 .addReg(AMDGPU::SCC);
1104 MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1248 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1382 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1572 CondPhysReg = AMDGPU::SCC;
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 292 case AMDGPU::SCC:
lib/Target/AMDGPU/SIInsertSkips.cpp 407 if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC) &&
lib/Target/AMDGPU/SIInstrInfo.cpp 543 if (SrcReg == AMDGPU::SCC) {
601 if (DestReg == AMDGPU::SCC) {
5014 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
5120 assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
5718 assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
5726 if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1)
5729 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
lib/Target/AMDGPU/SILowerControlFlow.cpp 140 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
207 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
lib/Target/AMDGPU/SILowerI1Copies.cpp 775 if (MO.isReg() && MO.getReg() == AMDGPU::SCC) {
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 314 RecalcRegs.insert(AMDGPU::SCC);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 563 .addReg(AMDGPU::SCC);
565 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
584 LiveRange &LR = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
936 LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 961 Reg == AMDGPU::SCC;