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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc28040 /* 58811*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
34133 /* 72474*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
47735 /*102815*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
47834 /*103017*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
52664 /*114247*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
52683 /*114306*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
52706 /*114361*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
52726 /*114421*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
52748 /*114473*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
52769 /*114524*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
52827 /*114656*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
59772 /*130722*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
60099 /*131500*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
60112 /*131533*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
60130 /*131589*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
60141 /*131621*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
60150 /*131654*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
62446 /*136572*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
62460 /*136597*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
62475 /*136626*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
62895 /*137218*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
63122 /*137772*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
63213 /*138016*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
63366 /*138319*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74848 /*165729*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74857 /*165754*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74864 /*165771*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74896 /*165869*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74903 /*165886*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74913 /*165911*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74920 /*165928*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74960 /*166043*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74972 /*166075*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74979 /*166092*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74992 /*166122*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
74999 /*166139*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75061 /*166268*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75076 /*166296*/ OPC_MorphNodeTo1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75095 /*166338*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75102 /*166355*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75112 /*166380*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75119 /*166397*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75148 /*166490*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75155 /*166507*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75332 /*166964*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75340 /*166989*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75356 /*167042*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75376 /*167109*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75384 /*167132*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75400 /*167185*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75417 /*167241*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75428 /*167275*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
75447 /*167339*/ OPC_EmitNode1, TARGET_VAL(AMDGPU::S_MOV_B32), 0,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc15515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
15530 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_MOV_B32,
17757 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17779 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17797 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17815 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17843 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17861 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17879 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
17992 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18014 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18032 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18050 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18660 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18678 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18702 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18720 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18785 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
18803 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::S_MOV_B32,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc59684 case AMDGPU::S_MOV_B32:
95460 { AMDGPU::S_MOV_B32, AMDGPU::S_MOV_B32_gfx6_gfx7, AMDGPU::S_MOV_B32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::S_MOV_B32_gfx10, (uint16_t)-1U },
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 113 return DAG.getMachineNode(AMDGPU::S_MOV_B32, SL, N->getValueType(0),
627 AMDGPU::S_MOV_B32, DL, MVT::i32,
630 CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
973 AMDGPU::S_MOV_B32, DL, MVT::i32,
1409 AMDGPU::S_MOV_B32, DL, MVT::i32,
1771 Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
1794 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, AddrHi),
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1426 unsigned Opcode = IsSgpr ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1546 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1604 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32));
1625 unsigned MovOpc = IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
1941 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 1028 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 346 SMovOp = AMDGPU::S_MOV_B32;
lib/Target/AMDGPU/SIFoldOperands.cpp 788 UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
922 return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
lib/Target/AMDGPU/SIFrameLowering.cpp 550 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
606 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
750 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
908 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
lib/Target/AMDGPU/SIISelLowering.cpp 3238 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3290 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3377 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3647 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3662 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
3727 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
6065 return {DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, GA), 0};
10283 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
10467 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
lib/Target/AMDGPU/SIInsertSkips.cpp 287 BuildMI(MBB, &MI, DL, TII->get(ST.isWave32() ? AMDGPU::S_MOV_B32
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1431 TII->get(ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64),
lib/Target/AMDGPU/SIInstrInfo.cpp 552 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
570 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
689 Opcode = AMDGPU::S_MOV_B32;
761 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
792 Opcode = AMDGPU::S_MOV_B32;
971 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
1385 MI.setDesc(get(AMDGPU::S_MOV_B32));
1540 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
2264 case AMDGPU::S_MOV_B32:
2320 case AMDGPU::S_MOV_B32:
2334 unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
3737 case AMDGPU::S_MOV_B32: {
3838 Opcode = (Size == 64) ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
4412 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
4494 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo)
4498 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi)
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 912 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1005 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1363 TII->get(AMDGPU::S_MOV_B32), Reg)
1445 if (!Def || Def->getOpcode() != AMDGPU::S_MOV_B32 ||
lib/Target/AMDGPU/SILowerI1Copies.cpp 465 MovOp = AMDGPU::S_MOV_B32;
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 64 case AMDGPU::S_MOV_B32:
81 case AMDGPU::S_MOV_B32: {
lib/Target/AMDGPU/SIRegisterInfo.cpp 366 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
1146 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg)
lib/Target/AMDGPU/SIShrinkInstructions.cpp 668 if (MI.getOpcode() == AMDGPU::S_MOV_B32) {