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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc52840 /*114684*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
52898 /*114832*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
57436 /*125608*/ OPC_EmitNode2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
57446 /*125634*/ OPC_EmitNode2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
57459 /*125671*/ OPC_EmitNode2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
60101 /*131507*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
60143 /*131628*/ OPC_EmitNode2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
75097 /*166345*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
75114 /*166387*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
75150 /*166497*/ OPC_MorphNodeTo2, TARGET_VAL(AMDGPU::S_AND_B32), 0,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc18664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_AND_B32,
18706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_AND_B32,
18789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::S_AND_B32,
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc58875 case AMDGPU::S_AND_B32:
95138 { AMDGPU::S_AND_B32, AMDGPU::S_AND_B32_gfx6_gfx7, AMDGPU::S_AND_B32_vi, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, (uint16_t)-1U, AMDGPU::S_AND_B32_gfx10, (uint16_t)-1U },
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 2068 Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 252 return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;
1339 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg)
1624 unsigned NewOpc = IsVGPR ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32;
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 675 AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
lib/Target/AMDGPU/SIFoldOperands.cpp 875 case AMDGPU::S_AND_B32:
1048 MI->getOpcode() == AMDGPU::S_AND_B32) {
1052 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32)));
lib/Target/AMDGPU/SIFrameLowering.cpp 797 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
lib/Target/AMDGPU/SIInsertSkips.cpp 295 Opcode = KillVal ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_AND_B32;
350 const unsigned And = IsWave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
lib/Target/AMDGPU/SIInstrInfo.cpp 3759 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64;
4331 ST.isWave32() ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
4847 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32, MDT);
4950 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B32),
4978 splitScalarNotBinop(Worklist, Inst, AMDGPU::S_AND_B32);
4988 splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_AND_B32);
lib/Target/AMDGPU/SILowerControlFlow.cpp 505 AndOpc = AMDGPU::S_AND_B32;
559 case AMDGPU::S_AND_B32:
lib/Target/AMDGPU/SILowerI1Copies.cpp 466 AndOp = AMDGPU::S_AND_B32;
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 117 case AMDGPU::S_AND_B32:
156 case AMDGPU::S_AND_B32:
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 195 const unsigned AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
lib/Target/AMDGPU/SIShrinkInstructions.cpp 331 if (Opc == AMDGPU::S_AND_B32) {
686 if (MI.getOpcode() == AMDGPU::S_AND_B32 ||
lib/Target/AMDGPU/SIWholeQuadMode.cpp 639 AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64),