|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 6595 Inst.addOperand(MCOperand::createReg(AArch64::XZR));
11256 case AArch64::XZR: OpKind = MCK_GPR64noip; break;
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc14891 MI->getOperand(0).getReg() == AArch64::XZR &&
14901 MI->getOperand(0).getReg() == AArch64::XZR &&
14913 MI->getOperand(0).getReg() == AArch64::XZR &&
14938 MI->getOperand(0).getReg() == AArch64::XZR &&
14950 MI->getOperand(0).getReg() == AArch64::XZR &&
14962 MI->getOperand(0).getReg() == AArch64::XZR &&
15176 MI->getOperand(0).getReg() == AArch64::XZR &&
15186 MI->getOperand(0).getReg() == AArch64::XZR &&
15198 MI->getOperand(0).getReg() == AArch64::XZR &&
15713 MI->getOperand(1).getReg() == AArch64::XZR &&
15714 MI->getOperand(2).getReg() == AArch64::XZR &&
15761 MI->getOperand(1).getReg() == AArch64::XZR &&
15762 MI->getOperand(2).getReg() == AArch64::XZR &&
17268 MI->getOperand(2).getReg() == AArch64::XZR &&
17370 MI->getOperand(3).getReg() == AArch64::XZR &&
17383 MI->getOperand(3).getReg() == AArch64::XZR &&
17396 MI->getOperand(3).getReg() == AArch64::XZR &&
17409 MI->getOperand(3).getReg() == AArch64::XZR &&
17422 MI->getOperand(3).getReg() == AArch64::XZR &&
17435 MI->getOperand(3).getReg() == AArch64::XZR &&
17448 MI->getOperand(3).getReg() == AArch64::XZR &&
17461 MI->getOperand(3).getReg() == AArch64::XZR &&
17522 MI->getOperand(3).getReg() == AArch64::XZR &&
17535 MI->getOperand(3).getReg() == AArch64::XZR &&
17548 MI->getOperand(3).getReg() == AArch64::XZR &&
17561 MI->getOperand(3).getReg() == AArch64::XZR &&
17574 MI->getOperand(3).getReg() == AArch64::XZR &&
17587 MI->getOperand(3).getReg() == AArch64::XZR &&
17600 MI->getOperand(3).getReg() == AArch64::XZR &&
17613 MI->getOperand(3).getReg() == AArch64::XZR &&
17946 MI->getOperand(3).getReg() == AArch64::XZR &&
17959 MI->getOperand(3).getReg() == AArch64::XZR &&
17972 MI->getOperand(3).getReg() == AArch64::XZR &&
17985 MI->getOperand(3).getReg() == AArch64::XZR &&
17998 MI->getOperand(3).getReg() == AArch64::XZR &&
18011 MI->getOperand(3).getReg() == AArch64::XZR &&
18024 MI->getOperand(3).getReg() == AArch64::XZR &&
18037 MI->getOperand(3).getReg() == AArch64::XZR &&
18146 MI->getOperand(3).getReg() == AArch64::XZR &&
18159 MI->getOperand(3).getReg() == AArch64::XZR &&
18172 MI->getOperand(3).getReg() == AArch64::XZR &&
18185 MI->getOperand(3).getReg() == AArch64::XZR &&
18198 MI->getOperand(3).getReg() == AArch64::XZR &&
18211 MI->getOperand(3).getReg() == AArch64::XZR &&
18224 MI->getOperand(3).getReg() == AArch64::XZR &&
18237 MI->getOperand(3).getReg() == AArch64::XZR &&
18250 MI->getOperand(3).getReg() == AArch64::XZR &&
18263 MI->getOperand(3).getReg() == AArch64::XZR &&
18276 MI->getOperand(3).getReg() == AArch64::XZR &&
18289 MI->getOperand(3).getReg() == AArch64::XZR &&
18302 MI->getOperand(3).getReg() == AArch64::XZR &&
18315 MI->getOperand(3).getReg() == AArch64::XZR &&
18328 MI->getOperand(3).getReg() == AArch64::XZR &&
18341 MI->getOperand(3).getReg() == AArch64::XZR &&
18386 MI->getOperand(5).getReg() == AArch64::XZR &&
18399 MI->getOperand(5).getReg() == AArch64::XZR &&
18412 MI->getOperand(5).getReg() == AArch64::XZR &&
18425 MI->getOperand(5).getReg() == AArch64::XZR &&
18486 MI->getOperand(3).getReg() == AArch64::XZR &&
18499 MI->getOperand(3).getReg() == AArch64::XZR &&
18512 MI->getOperand(3).getReg() == AArch64::XZR &&
18525 MI->getOperand(3).getReg() == AArch64::XZR &&
18538 MI->getOperand(3).getReg() == AArch64::XZR &&
18551 MI->getOperand(3).getReg() == AArch64::XZR &&
18564 MI->getOperand(3).getReg() == AArch64::XZR &&
18577 MI->getOperand(3).getReg() == AArch64::XZR &&
18590 MI->getOperand(3).getReg() == AArch64::XZR &&
18603 MI->getOperand(3).getReg() == AArch64::XZR &&
18616 MI->getOperand(3).getReg() == AArch64::XZR &&
18629 MI->getOperand(3).getReg() == AArch64::XZR &&
18642 MI->getOperand(3).getReg() == AArch64::XZR &&
18655 MI->getOperand(3).getReg() == AArch64::XZR &&
18668 MI->getOperand(3).getReg() == AArch64::XZR &&
18697 MI->getOperand(5).getReg() == AArch64::XZR &&
18710 MI->getOperand(5).getReg() == AArch64::XZR &&
18723 MI->getOperand(5).getReg() == AArch64::XZR &&
18736 MI->getOperand(5).getReg() == AArch64::XZR &&
18797 MI->getOperand(3).getReg() == AArch64::XZR &&
18810 MI->getOperand(3).getReg() == AArch64::XZR &&
18823 MI->getOperand(3).getReg() == AArch64::XZR &&
18836 MI->getOperand(3).getReg() == AArch64::XZR &&
18849 MI->getOperand(3).getReg() == AArch64::XZR &&
18862 MI->getOperand(3).getReg() == AArch64::XZR &&
18875 MI->getOperand(3).getReg() == AArch64::XZR &&
18888 MI->getOperand(3).getReg() == AArch64::XZR &&
18901 MI->getOperand(3).getReg() == AArch64::XZR &&
18914 MI->getOperand(3).getReg() == AArch64::XZR &&
18927 MI->getOperand(3).getReg() == AArch64::XZR &&
18940 MI->getOperand(3).getReg() == AArch64::XZR &&
18953 MI->getOperand(3).getReg() == AArch64::XZR &&
18966 MI->getOperand(3).getReg() == AArch64::XZR &&
18979 MI->getOperand(3).getReg() == AArch64::XZR &&
19008 MI->getOperand(5).getReg() == AArch64::XZR &&
19021 MI->getOperand(5).getReg() == AArch64::XZR &&
19034 MI->getOperand(5).getReg() == AArch64::XZR &&
19047 MI->getOperand(5).getReg() == AArch64::XZR &&
19092 MI->getOperand(3).getReg() == AArch64::XZR &&
19105 MI->getOperand(3).getReg() == AArch64::XZR &&
19118 MI->getOperand(3).getReg() == AArch64::XZR &&
19131 MI->getOperand(3).getReg() == AArch64::XZR &&
19144 MI->getOperand(3).getReg() == AArch64::XZR &&
19157 MI->getOperand(3).getReg() == AArch64::XZR &&
19170 MI->getOperand(3).getReg() == AArch64::XZR &&
19199 MI->getOperand(3).getReg() == AArch64::XZR &&
19212 MI->getOperand(3).getReg() == AArch64::XZR &&
19225 MI->getOperand(3).getReg() == AArch64::XZR &&
19238 MI->getOperand(3).getReg() == AArch64::XZR &&
19251 MI->getOperand(3).getReg() == AArch64::XZR &&
19264 MI->getOperand(3).getReg() == AArch64::XZR &&
19277 MI->getOperand(3).getReg() == AArch64::XZR &&
19290 MI->getOperand(3).getReg() == AArch64::XZR &&
19319 MI->getOperand(5).getReg() == AArch64::XZR &&
19332 MI->getOperand(5).getReg() == AArch64::XZR &&
19345 MI->getOperand(5).getReg() == AArch64::XZR &&
19358 MI->getOperand(5).getReg() == AArch64::XZR &&
19432 MI->getOperand(0).getReg() == AArch64::XZR &&
19458 MI->getOperand(0).getReg() == AArch64::XZR &&
19662 MI->getOperand(0).getReg() == AArch64::XZR &&
19688 MI->getOperand(0).getReg() == AArch64::XZR &&
19766 MI->getOperand(0).getReg() == AArch64::XZR &&
19792 MI->getOperand(0).getReg() == AArch64::XZR &&
19811 MI->getOperand(3).getReg() == AArch64::XZR &&
19826 MI->getOperand(3).getReg() == AArch64::XZR &&
19841 MI->getOperand(3).getReg() == AArch64::XZR &&
19856 MI->getOperand(3).getReg() == AArch64::XZR &&
19871 MI->getOperand(3).getReg() == AArch64::XZR &&
19886 MI->getOperand(3).getReg() == AArch64::XZR &&
19901 MI->getOperand(3).getReg() == AArch64::XZR &&
19916 MI->getOperand(3).getReg() == AArch64::XZR &&
19931 MI->getOperand(3).getReg() == AArch64::XZR &&
19946 MI->getOperand(3).getReg() == AArch64::XZR &&
19961 MI->getOperand(3).getReg() == AArch64::XZR &&
19976 MI->getOperand(3).getReg() == AArch64::XZR &&
19991 MI->getOperand(3).getReg() == AArch64::XZR &&
20006 MI->getOperand(3).getReg() == AArch64::XZR &&
20021 MI->getOperand(3).getReg() == AArch64::XZR &&
20036 MI->getOperand(3).getReg() == AArch64::XZR &&
20412 MI->getOperand(3).getReg() == AArch64::XZR &&
20427 MI->getOperand(3).getReg() == AArch64::XZR &&
20458 MI->getOperand(3).getReg() == AArch64::XZR &&
20489 MI->getOperand(3).getReg() == AArch64::XZR &&
20504 MI->getOperand(3).getReg() == AArch64::XZR &&
20519 MI->getOperand(3).getReg() == AArch64::XZR &&
20534 MI->getOperand(3).getReg() == AArch64::XZR &&
20549 MI->getOperand(3).getReg() == AArch64::XZR &&
20564 MI->getOperand(3).getReg() == AArch64::XZR &&
20579 MI->getOperand(3).getReg() == AArch64::XZR &&
20610 MI->getOperand(3).getReg() == AArch64::XZR &&
20625 MI->getOperand(3).getReg() == AArch64::XZR &&
21265 MI->getOperand(0).getReg() == AArch64::XZR &&
21291 MI->getOperand(0).getReg() == AArch64::XZR &&
21369 MI->getOperand(0).getReg() == AArch64::XZR &&
21395 MI->getOperand(0).getReg() == AArch64::XZR &&
21473 MI->getOperand(0).getReg() == AArch64::XZR &&
21499 MI->getOperand(0).getReg() == AArch64::XZR &&
21694 MI->getOperand(0).getReg() == AArch64::XZR &&
21720 MI->getOperand(0).getReg() == AArch64::XZR &&
21798 MI->getOperand(0).getReg() == AArch64::XZR &&
21824 MI->getOperand(0).getReg() == AArch64::XZR &&
22039 MI->getOperand(3).getReg() == AArch64::XZR) {
22067 MI->getOperand(3).getReg() == AArch64::XZR) {
22136 MI->getOperand(1).getReg() == AArch64::XZR &&
22148 MI->getOperand(1).getReg() == AArch64::XZR &&
22216 MI->getOperand(1).getReg() == AArch64::XZR &&
22649 MI->getOperand(1).getReg() == AArch64::XZR &&
22673 MI->getOperand(1).getReg() == AArch64::XZR &&
22860 MI->getOperand(3).getReg() == AArch64::XZR) {
22874 MI->getOperand(3).getReg() == AArch64::XZR) {
23638 MI->getOperand(3).getReg() == AArch64::XZR &&
23651 MI->getOperand(3).getReg() == AArch64::XZR &&
23664 MI->getOperand(3).getReg() == AArch64::XZR &&
23677 MI->getOperand(3).getReg() == AArch64::XZR &&
23690 MI->getOperand(3).getReg() == AArch64::XZR &&
23703 MI->getOperand(3).getReg() == AArch64::XZR &&
23716 MI->getOperand(3).getReg() == AArch64::XZR &&
23729 MI->getOperand(3).getReg() == AArch64::XZR &&
23790 MI->getOperand(3).getReg() == AArch64::XZR &&
23803 MI->getOperand(3).getReg() == AArch64::XZR &&
23816 MI->getOperand(3).getReg() == AArch64::XZR &&
23829 MI->getOperand(3).getReg() == AArch64::XZR &&
23842 MI->getOperand(3).getReg() == AArch64::XZR &&
23855 MI->getOperand(3).getReg() == AArch64::XZR &&
23868 MI->getOperand(3).getReg() == AArch64::XZR &&
23881 MI->getOperand(3).getReg() == AArch64::XZR &&
23894 MI->getOperand(3).getReg() == AArch64::XZR &&
23907 MI->getOperand(3).getReg() == AArch64::XZR &&
23920 MI->getOperand(3).getReg() == AArch64::XZR &&
23933 MI->getOperand(3).getReg() == AArch64::XZR &&
23946 MI->getOperand(3).getReg() == AArch64::XZR &&
23959 MI->getOperand(3).getReg() == AArch64::XZR &&
23972 MI->getOperand(3).getReg() == AArch64::XZR &&
23985 MI->getOperand(3).getReg() == AArch64::XZR &&
23998 MI->getOperand(3).getReg() == AArch64::XZR &&
24011 MI->getOperand(3).getReg() == AArch64::XZR &&
24024 MI->getOperand(3).getReg() == AArch64::XZR &&
24037 MI->getOperand(3).getReg() == AArch64::XZR &&
24050 MI->getOperand(3).getReg() == AArch64::XZR &&
24063 MI->getOperand(3).getReg() == AArch64::XZR &&
24076 MI->getOperand(3).getReg() == AArch64::XZR &&
24089 MI->getOperand(3).getReg() == AArch64::XZR &&
24134 MI->getOperand(4).getReg() == AArch64::XZR &&
24147 MI->getOperand(4).getReg() == AArch64::XZR &&
24160 MI->getOperand(4).getReg() == AArch64::XZR &&
24173 MI->getOperand(4).getReg() == AArch64::XZR &&
24248 MI->getOperand(3).getReg() == AArch64::XZR &&
24261 MI->getOperand(3).getReg() == AArch64::XZR &&
24274 MI->getOperand(3).getReg() == AArch64::XZR &&
24287 MI->getOperand(3).getReg() == AArch64::XZR &&
24300 MI->getOperand(3).getReg() == AArch64::XZR &&
24313 MI->getOperand(3).getReg() == AArch64::XZR &&
24326 MI->getOperand(3).getReg() == AArch64::XZR &&
24355 MI->getOperand(4).getReg() == AArch64::XZR &&
24368 MI->getOperand(4).getReg() == AArch64::XZR &&
24381 MI->getOperand(4).getReg() == AArch64::XZR &&
24394 MI->getOperand(4).getReg() == AArch64::XZR &&
24455 MI->getOperand(3).getReg() == AArch64::XZR &&
24468 MI->getOperand(3).getReg() == AArch64::XZR &&
24481 MI->getOperand(3).getReg() == AArch64::XZR &&
24494 MI->getOperand(3).getReg() == AArch64::XZR &&
24507 MI->getOperand(3).getReg() == AArch64::XZR &&
24520 MI->getOperand(3).getReg() == AArch64::XZR &&
24533 MI->getOperand(3).getReg() == AArch64::XZR &&
24562 MI->getOperand(4).getReg() == AArch64::XZR &&
24575 MI->getOperand(4).getReg() == AArch64::XZR &&
24588 MI->getOperand(4).getReg() == AArch64::XZR &&
24601 MI->getOperand(4).getReg() == AArch64::XZR &&
24646 MI->getOperand(3).getReg() == AArch64::XZR &&
24659 MI->getOperand(3).getReg() == AArch64::XZR &&
24672 MI->getOperand(3).getReg() == AArch64::XZR &&
24685 MI->getOperand(3).getReg() == AArch64::XZR &&
24698 MI->getOperand(3).getReg() == AArch64::XZR &&
24711 MI->getOperand(3).getReg() == AArch64::XZR &&
24724 MI->getOperand(3).getReg() == AArch64::XZR &&
24769 MI->getOperand(4).getReg() == AArch64::XZR &&
24782 MI->getOperand(4).getReg() == AArch64::XZR &&
24795 MI->getOperand(4).getReg() == AArch64::XZR &&
24808 MI->getOperand(4).getReg() == AArch64::XZR &&
25000 MI->getOperand(3).getReg() == AArch64::XZR &&
25015 MI->getOperand(3).getReg() == AArch64::XZR &&
25046 MI->getOperand(3).getReg() == AArch64::XZR &&
25077 MI->getOperand(3).getReg() == AArch64::XZR &&
25092 MI->getOperand(3).getReg() == AArch64::XZR &&
25123 MI->getOperand(3).getReg() == AArch64::XZR &&
25138 MI->getOperand(3).getReg() == AArch64::XZR &&
25823 MI->getOperand(0).getReg() == AArch64::XZR &&
25833 MI->getOperand(0).getReg() == AArch64::XZR &&
25845 MI->getOperand(0).getReg() == AArch64::XZR &&
25857 MI->getOperand(1).getReg() == AArch64::XZR &&
25869 MI->getOperand(1).getReg() == AArch64::XZR &&
25892 MI->getOperand(0).getReg() == AArch64::XZR &&
25904 MI->getOperand(0).getReg() == AArch64::XZR &&
25916 MI->getOperand(0).getReg() == AArch64::XZR &&
26008 MI->getOperand(1).getReg() == AArch64::XZR &&
26020 MI->getOperand(1).getReg() == AArch64::XZR &&
26071 MI->getOperand(4).getReg() == AArch64::XZR) {
26176 MI->getOperand(3).getReg() == AArch64::XZR) {
26214 MI->getOperand(3).getReg() == AArch64::XZR) {
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc15607 MI->getOperand(0).getReg() == AArch64::XZR &&
15617 MI->getOperand(0).getReg() == AArch64::XZR &&
15629 MI->getOperand(0).getReg() == AArch64::XZR &&
15654 MI->getOperand(0).getReg() == AArch64::XZR &&
15666 MI->getOperand(0).getReg() == AArch64::XZR &&
15678 MI->getOperand(0).getReg() == AArch64::XZR &&
15892 MI->getOperand(0).getReg() == AArch64::XZR &&
15902 MI->getOperand(0).getReg() == AArch64::XZR &&
15914 MI->getOperand(0).getReg() == AArch64::XZR &&
16429 MI->getOperand(1).getReg() == AArch64::XZR &&
16430 MI->getOperand(2).getReg() == AArch64::XZR &&
16477 MI->getOperand(1).getReg() == AArch64::XZR &&
16478 MI->getOperand(2).getReg() == AArch64::XZR &&
17984 MI->getOperand(2).getReg() == AArch64::XZR &&
18086 MI->getOperand(3).getReg() == AArch64::XZR &&
18099 MI->getOperand(3).getReg() == AArch64::XZR &&
18112 MI->getOperand(3).getReg() == AArch64::XZR &&
18125 MI->getOperand(3).getReg() == AArch64::XZR &&
18138 MI->getOperand(3).getReg() == AArch64::XZR &&
18151 MI->getOperand(3).getReg() == AArch64::XZR &&
18164 MI->getOperand(3).getReg() == AArch64::XZR &&
18177 MI->getOperand(3).getReg() == AArch64::XZR &&
18238 MI->getOperand(3).getReg() == AArch64::XZR &&
18251 MI->getOperand(3).getReg() == AArch64::XZR &&
18264 MI->getOperand(3).getReg() == AArch64::XZR &&
18277 MI->getOperand(3).getReg() == AArch64::XZR &&
18290 MI->getOperand(3).getReg() == AArch64::XZR &&
18303 MI->getOperand(3).getReg() == AArch64::XZR &&
18316 MI->getOperand(3).getReg() == AArch64::XZR &&
18329 MI->getOperand(3).getReg() == AArch64::XZR &&
18662 MI->getOperand(3).getReg() == AArch64::XZR &&
18675 MI->getOperand(3).getReg() == AArch64::XZR &&
18688 MI->getOperand(3).getReg() == AArch64::XZR &&
18701 MI->getOperand(3).getReg() == AArch64::XZR &&
18714 MI->getOperand(3).getReg() == AArch64::XZR &&
18727 MI->getOperand(3).getReg() == AArch64::XZR &&
18740 MI->getOperand(3).getReg() == AArch64::XZR &&
18753 MI->getOperand(3).getReg() == AArch64::XZR &&
18862 MI->getOperand(3).getReg() == AArch64::XZR &&
18875 MI->getOperand(3).getReg() == AArch64::XZR &&
18888 MI->getOperand(3).getReg() == AArch64::XZR &&
18901 MI->getOperand(3).getReg() == AArch64::XZR &&
18914 MI->getOperand(3).getReg() == AArch64::XZR &&
18927 MI->getOperand(3).getReg() == AArch64::XZR &&
18940 MI->getOperand(3).getReg() == AArch64::XZR &&
18953 MI->getOperand(3).getReg() == AArch64::XZR &&
18966 MI->getOperand(3).getReg() == AArch64::XZR &&
18979 MI->getOperand(3).getReg() == AArch64::XZR &&
18992 MI->getOperand(3).getReg() == AArch64::XZR &&
19005 MI->getOperand(3).getReg() == AArch64::XZR &&
19018 MI->getOperand(3).getReg() == AArch64::XZR &&
19031 MI->getOperand(3).getReg() == AArch64::XZR &&
19044 MI->getOperand(3).getReg() == AArch64::XZR &&
19057 MI->getOperand(3).getReg() == AArch64::XZR &&
19102 MI->getOperand(5).getReg() == AArch64::XZR &&
19115 MI->getOperand(5).getReg() == AArch64::XZR &&
19128 MI->getOperand(5).getReg() == AArch64::XZR &&
19141 MI->getOperand(5).getReg() == AArch64::XZR &&
19202 MI->getOperand(3).getReg() == AArch64::XZR &&
19215 MI->getOperand(3).getReg() == AArch64::XZR &&
19228 MI->getOperand(3).getReg() == AArch64::XZR &&
19241 MI->getOperand(3).getReg() == AArch64::XZR &&
19254 MI->getOperand(3).getReg() == AArch64::XZR &&
19267 MI->getOperand(3).getReg() == AArch64::XZR &&
19280 MI->getOperand(3).getReg() == AArch64::XZR &&
19293 MI->getOperand(3).getReg() == AArch64::XZR &&
19306 MI->getOperand(3).getReg() == AArch64::XZR &&
19319 MI->getOperand(3).getReg() == AArch64::XZR &&
19332 MI->getOperand(3).getReg() == AArch64::XZR &&
19345 MI->getOperand(3).getReg() == AArch64::XZR &&
19358 MI->getOperand(3).getReg() == AArch64::XZR &&
19371 MI->getOperand(3).getReg() == AArch64::XZR &&
19384 MI->getOperand(3).getReg() == AArch64::XZR &&
19413 MI->getOperand(5).getReg() == AArch64::XZR &&
19426 MI->getOperand(5).getReg() == AArch64::XZR &&
19439 MI->getOperand(5).getReg() == AArch64::XZR &&
19452 MI->getOperand(5).getReg() == AArch64::XZR &&
19513 MI->getOperand(3).getReg() == AArch64::XZR &&
19526 MI->getOperand(3).getReg() == AArch64::XZR &&
19539 MI->getOperand(3).getReg() == AArch64::XZR &&
19552 MI->getOperand(3).getReg() == AArch64::XZR &&
19565 MI->getOperand(3).getReg() == AArch64::XZR &&
19578 MI->getOperand(3).getReg() == AArch64::XZR &&
19591 MI->getOperand(3).getReg() == AArch64::XZR &&
19604 MI->getOperand(3).getReg() == AArch64::XZR &&
19617 MI->getOperand(3).getReg() == AArch64::XZR &&
19630 MI->getOperand(3).getReg() == AArch64::XZR &&
19643 MI->getOperand(3).getReg() == AArch64::XZR &&
19656 MI->getOperand(3).getReg() == AArch64::XZR &&
19669 MI->getOperand(3).getReg() == AArch64::XZR &&
19682 MI->getOperand(3).getReg() == AArch64::XZR &&
19695 MI->getOperand(3).getReg() == AArch64::XZR &&
19724 MI->getOperand(5).getReg() == AArch64::XZR &&
19737 MI->getOperand(5).getReg() == AArch64::XZR &&
19750 MI->getOperand(5).getReg() == AArch64::XZR &&
19763 MI->getOperand(5).getReg() == AArch64::XZR &&
19808 MI->getOperand(3).getReg() == AArch64::XZR &&
19821 MI->getOperand(3).getReg() == AArch64::XZR &&
19834 MI->getOperand(3).getReg() == AArch64::XZR &&
19847 MI->getOperand(3).getReg() == AArch64::XZR &&
19860 MI->getOperand(3).getReg() == AArch64::XZR &&
19873 MI->getOperand(3).getReg() == AArch64::XZR &&
19886 MI->getOperand(3).getReg() == AArch64::XZR &&
19915 MI->getOperand(3).getReg() == AArch64::XZR &&
19928 MI->getOperand(3).getReg() == AArch64::XZR &&
19941 MI->getOperand(3).getReg() == AArch64::XZR &&
19954 MI->getOperand(3).getReg() == AArch64::XZR &&
19967 MI->getOperand(3).getReg() == AArch64::XZR &&
19980 MI->getOperand(3).getReg() == AArch64::XZR &&
19993 MI->getOperand(3).getReg() == AArch64::XZR &&
20006 MI->getOperand(3).getReg() == AArch64::XZR &&
20035 MI->getOperand(5).getReg() == AArch64::XZR &&
20048 MI->getOperand(5).getReg() == AArch64::XZR &&
20061 MI->getOperand(5).getReg() == AArch64::XZR &&
20074 MI->getOperand(5).getReg() == AArch64::XZR &&
20148 MI->getOperand(0).getReg() == AArch64::XZR &&
20174 MI->getOperand(0).getReg() == AArch64::XZR &&
20378 MI->getOperand(0).getReg() == AArch64::XZR &&
20404 MI->getOperand(0).getReg() == AArch64::XZR &&
20482 MI->getOperand(0).getReg() == AArch64::XZR &&
20508 MI->getOperand(0).getReg() == AArch64::XZR &&
20527 MI->getOperand(3).getReg() == AArch64::XZR &&
20542 MI->getOperand(3).getReg() == AArch64::XZR &&
20557 MI->getOperand(3).getReg() == AArch64::XZR &&
20572 MI->getOperand(3).getReg() == AArch64::XZR &&
20587 MI->getOperand(3).getReg() == AArch64::XZR &&
20602 MI->getOperand(3).getReg() == AArch64::XZR &&
20617 MI->getOperand(3).getReg() == AArch64::XZR &&
20632 MI->getOperand(3).getReg() == AArch64::XZR &&
20647 MI->getOperand(3).getReg() == AArch64::XZR &&
20662 MI->getOperand(3).getReg() == AArch64::XZR &&
20677 MI->getOperand(3).getReg() == AArch64::XZR &&
20692 MI->getOperand(3).getReg() == AArch64::XZR &&
20707 MI->getOperand(3).getReg() == AArch64::XZR &&
20722 MI->getOperand(3).getReg() == AArch64::XZR &&
20737 MI->getOperand(3).getReg() == AArch64::XZR &&
20752 MI->getOperand(3).getReg() == AArch64::XZR &&
21128 MI->getOperand(3).getReg() == AArch64::XZR &&
21143 MI->getOperand(3).getReg() == AArch64::XZR &&
21174 MI->getOperand(3).getReg() == AArch64::XZR &&
21205 MI->getOperand(3).getReg() == AArch64::XZR &&
21220 MI->getOperand(3).getReg() == AArch64::XZR &&
21235 MI->getOperand(3).getReg() == AArch64::XZR &&
21250 MI->getOperand(3).getReg() == AArch64::XZR &&
21265 MI->getOperand(3).getReg() == AArch64::XZR &&
21280 MI->getOperand(3).getReg() == AArch64::XZR &&
21295 MI->getOperand(3).getReg() == AArch64::XZR &&
21326 MI->getOperand(3).getReg() == AArch64::XZR &&
21341 MI->getOperand(3).getReg() == AArch64::XZR &&
21981 MI->getOperand(0).getReg() == AArch64::XZR &&
22007 MI->getOperand(0).getReg() == AArch64::XZR &&
22085 MI->getOperand(0).getReg() == AArch64::XZR &&
22111 MI->getOperand(0).getReg() == AArch64::XZR &&
22189 MI->getOperand(0).getReg() == AArch64::XZR &&
22215 MI->getOperand(0).getReg() == AArch64::XZR &&
22410 MI->getOperand(0).getReg() == AArch64::XZR &&
22436 MI->getOperand(0).getReg() == AArch64::XZR &&
22514 MI->getOperand(0).getReg() == AArch64::XZR &&
22540 MI->getOperand(0).getReg() == AArch64::XZR &&
22755 MI->getOperand(3).getReg() == AArch64::XZR) {
22783 MI->getOperand(3).getReg() == AArch64::XZR) {
22852 MI->getOperand(1).getReg() == AArch64::XZR &&
22864 MI->getOperand(1).getReg() == AArch64::XZR &&
22932 MI->getOperand(1).getReg() == AArch64::XZR &&
23365 MI->getOperand(1).getReg() == AArch64::XZR &&
23389 MI->getOperand(1).getReg() == AArch64::XZR &&
23576 MI->getOperand(3).getReg() == AArch64::XZR) {
23590 MI->getOperand(3).getReg() == AArch64::XZR) {
24354 MI->getOperand(3).getReg() == AArch64::XZR &&
24367 MI->getOperand(3).getReg() == AArch64::XZR &&
24380 MI->getOperand(3).getReg() == AArch64::XZR &&
24393 MI->getOperand(3).getReg() == AArch64::XZR &&
24406 MI->getOperand(3).getReg() == AArch64::XZR &&
24419 MI->getOperand(3).getReg() == AArch64::XZR &&
24432 MI->getOperand(3).getReg() == AArch64::XZR &&
24445 MI->getOperand(3).getReg() == AArch64::XZR &&
24506 MI->getOperand(3).getReg() == AArch64::XZR &&
24519 MI->getOperand(3).getReg() == AArch64::XZR &&
24532 MI->getOperand(3).getReg() == AArch64::XZR &&
24545 MI->getOperand(3).getReg() == AArch64::XZR &&
24558 MI->getOperand(3).getReg() == AArch64::XZR &&
24571 MI->getOperand(3).getReg() == AArch64::XZR &&
24584 MI->getOperand(3).getReg() == AArch64::XZR &&
24597 MI->getOperand(3).getReg() == AArch64::XZR &&
24610 MI->getOperand(3).getReg() == AArch64::XZR &&
24623 MI->getOperand(3).getReg() == AArch64::XZR &&
24636 MI->getOperand(3).getReg() == AArch64::XZR &&
24649 MI->getOperand(3).getReg() == AArch64::XZR &&
24662 MI->getOperand(3).getReg() == AArch64::XZR &&
24675 MI->getOperand(3).getReg() == AArch64::XZR &&
24688 MI->getOperand(3).getReg() == AArch64::XZR &&
24701 MI->getOperand(3).getReg() == AArch64::XZR &&
24714 MI->getOperand(3).getReg() == AArch64::XZR &&
24727 MI->getOperand(3).getReg() == AArch64::XZR &&
24740 MI->getOperand(3).getReg() == AArch64::XZR &&
24753 MI->getOperand(3).getReg() == AArch64::XZR &&
24766 MI->getOperand(3).getReg() == AArch64::XZR &&
24779 MI->getOperand(3).getReg() == AArch64::XZR &&
24792 MI->getOperand(3).getReg() == AArch64::XZR &&
24805 MI->getOperand(3).getReg() == AArch64::XZR &&
24850 MI->getOperand(4).getReg() == AArch64::XZR &&
24863 MI->getOperand(4).getReg() == AArch64::XZR &&
24876 MI->getOperand(4).getReg() == AArch64::XZR &&
24889 MI->getOperand(4).getReg() == AArch64::XZR &&
24964 MI->getOperand(3).getReg() == AArch64::XZR &&
24977 MI->getOperand(3).getReg() == AArch64::XZR &&
24990 MI->getOperand(3).getReg() == AArch64::XZR &&
25003 MI->getOperand(3).getReg() == AArch64::XZR &&
25016 MI->getOperand(3).getReg() == AArch64::XZR &&
25029 MI->getOperand(3).getReg() == AArch64::XZR &&
25042 MI->getOperand(3).getReg() == AArch64::XZR &&
25071 MI->getOperand(4).getReg() == AArch64::XZR &&
25084 MI->getOperand(4).getReg() == AArch64::XZR &&
25097 MI->getOperand(4).getReg() == AArch64::XZR &&
25110 MI->getOperand(4).getReg() == AArch64::XZR &&
25171 MI->getOperand(3).getReg() == AArch64::XZR &&
25184 MI->getOperand(3).getReg() == AArch64::XZR &&
25197 MI->getOperand(3).getReg() == AArch64::XZR &&
25210 MI->getOperand(3).getReg() == AArch64::XZR &&
25223 MI->getOperand(3).getReg() == AArch64::XZR &&
25236 MI->getOperand(3).getReg() == AArch64::XZR &&
25249 MI->getOperand(3).getReg() == AArch64::XZR &&
25278 MI->getOperand(4).getReg() == AArch64::XZR &&
25291 MI->getOperand(4).getReg() == AArch64::XZR &&
25304 MI->getOperand(4).getReg() == AArch64::XZR &&
25317 MI->getOperand(4).getReg() == AArch64::XZR &&
25362 MI->getOperand(3).getReg() == AArch64::XZR &&
25375 MI->getOperand(3).getReg() == AArch64::XZR &&
25388 MI->getOperand(3).getReg() == AArch64::XZR &&
25401 MI->getOperand(3).getReg() == AArch64::XZR &&
25414 MI->getOperand(3).getReg() == AArch64::XZR &&
25427 MI->getOperand(3).getReg() == AArch64::XZR &&
25440 MI->getOperand(3).getReg() == AArch64::XZR &&
25485 MI->getOperand(4).getReg() == AArch64::XZR &&
25498 MI->getOperand(4).getReg() == AArch64::XZR &&
25511 MI->getOperand(4).getReg() == AArch64::XZR &&
25524 MI->getOperand(4).getReg() == AArch64::XZR &&
25716 MI->getOperand(3).getReg() == AArch64::XZR &&
25731 MI->getOperand(3).getReg() == AArch64::XZR &&
25762 MI->getOperand(3).getReg() == AArch64::XZR &&
25793 MI->getOperand(3).getReg() == AArch64::XZR &&
25808 MI->getOperand(3).getReg() == AArch64::XZR &&
25839 MI->getOperand(3).getReg() == AArch64::XZR &&
25854 MI->getOperand(3).getReg() == AArch64::XZR &&
26539 MI->getOperand(0).getReg() == AArch64::XZR &&
26549 MI->getOperand(0).getReg() == AArch64::XZR &&
26561 MI->getOperand(0).getReg() == AArch64::XZR &&
26573 MI->getOperand(1).getReg() == AArch64::XZR &&
26585 MI->getOperand(1).getReg() == AArch64::XZR &&
26608 MI->getOperand(0).getReg() == AArch64::XZR &&
26620 MI->getOperand(0).getReg() == AArch64::XZR &&
26632 MI->getOperand(0).getReg() == AArch64::XZR &&
26724 MI->getOperand(1).getReg() == AArch64::XZR &&
26736 MI->getOperand(1).getReg() == AArch64::XZR &&
26787 MI->getOperand(4).getReg() == AArch64::XZR) {
26892 MI->getOperand(3).getReg() == AArch64::XZR) {
26930 MI->getOperand(3).getReg() == AArch64::XZR) {
gen/lib/Target/AArch64/AArch64GenDAGISel.inc71324 /*170788*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71347 /*170831*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71369 /*170872*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71391 /*170913*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71413 /*170954*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71435 /*170995*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71457 /*171036*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71484 /*171094*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71511 /*171152*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71537 /*171208*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71563 /*171264*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71589 /*171320*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71615 /*171376*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
71641 /*171432*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
86695 /*200173*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
86707 /*200195*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
86728 /*200238*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
86740 /*200260*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
86765 /*200314*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
86876 /*200532*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
88511 /*203736*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92604 /*210810*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92624 /*210850*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92646 /*210896*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92657 /*210917*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92677 /*210959*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92688 /*210980*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92712 /*211033*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92729 /*211069*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92906 /*211414*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92907 /*211417*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92933 /*211481*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
92934 /*211484*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
93135 /*211892*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
93162 /*211948*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
93189 /*212013*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
93216 /*212078*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98460 /*221882*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98471 /*221907*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98482 /*221932*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98493 /*221957*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98504 /*221982*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98701 /*222424*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98712 /*222449*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98723 /*222474*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98734 /*222499*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
98745 /*222524*/ OPC_EmitRegister, MVT::i64, AArch64::XZR,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 4198 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
4233 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
4262 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
4291 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
4440 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
5246 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
5266 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
5294 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
5322 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
5344 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
5366 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
5380 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
7120 GIR_AddRegister, /*InsnID*/0, AArch64::XZR, /*AddRegisterRegFlags*/0,
16385 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt
16445 GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, AArch64::XZR, // Rt
19000 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19025 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19050 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19075 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19100 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19534 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19559 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19584 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19609 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
19634 GIR_AddRegister, /*InsnID*/1, AArch64::XZR, /*AddRegisterRegFlags*/0,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18213 || MI.getOperand(1).getReg() == AArch64::XZR
18302 || MI.getOperand(1).getReg() == AArch64::XZR
18339 || MI.getOperand(1).getReg() == AArch64::XZR
29951 || MI.getOperand(1).getReg() == AArch64::XZR
30040 || MI.getOperand(1).getReg() == AArch64::XZR
30077 || MI.getOperand(1).getReg() == AArch64::XZR
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 2430 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP,
2450 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR,
2480 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::XZR,
3789 { AArch64::XZR, 31U },
4068 { AArch64::XZR, 31U },
6853 static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 };
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc20608 MI->getOperand(1).getReg() == AArch64::XZR)
20935 MI->getOperand(1).getReg() == AArch64::XZR)
21389 MI->getOperand(1).getReg() == AArch64::XZR)
21560 MI->getOperand(1).getReg() == AArch64::XZR)
lib/Target/AArch64/AArch64A53Fix835769.cpp 69 return MI->getOperand(3).getReg() != AArch64::XZR;
lib/Target/AArch64/AArch64AsmPrinter.cpp 315 .addReg(AArch64::XZR)
386 .addReg(AArch64::XZR)
417 .addReg(AArch64::XZR)
581 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
895 FMov.addOperand(MCOperand::createReg(AArch64::XZR));
lib/Target/AArch64/AArch64CondBrTuning.cpp 103 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
lib/Target/AArch64/AArch64ConditionalCompares.cpp 260 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 127 if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
167 else if (RC->contains(AArch64::XZR))
168 NewReg = AArch64::XZR;
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 115 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
137 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
286 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
294 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
649 AArch64::XZR, NextMBBI);
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 771 .addReg(AArch64::XZR)
786 .addReg(AArch64::XZR)
lib/Target/AArch64/AArch64FastISel.cpp 390 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
560 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1341 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1386 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1428 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1447 assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR &&
1448 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR);
1473 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
2208 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2212 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
3792 emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
3805 emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
4050 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
4066 AArch64::XZR, /*IsKill=*/true);
4076 AArch64::XZR, /*IsKill=*/true);
4972 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
5133 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR)
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2556 ZeroReg = AArch64::XZR;
2949 CurDAG->getEntryNode(), SDLoc(Node), AArch64::XZR, MVT::i64);
lib/Target/AArch64/AArch64ISelLowering.cpp 6085 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
10729 ZeroReg = AArch64::XZR;
10924 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
11099 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
lib/Target/AArch64/AArch64InstrInfo.cpp 462 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
480 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR)
580 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
614 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
702 MI.getOperand(1).getReg() == AArch64::XZR))
1092 if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR))
1191 CmpInstr.definesRegister(AArch64::XZR)) {
1591 return MI.getOperand(1).getReg() == AArch64::XZR;
1611 if (MI.getOperand(1).getReg() == AArch64::XZR) {
2509 .addReg(AArch64::XZR)
2544 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) {
2551 } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGP()) {
2558 .addReg(AArch64::XZR)
2626 AArch64::XZR, Indices);
3705 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULADDX_OP1);
3706 setFound(AArch64::MADDXrrr, 2, AArch64::XZR, MCP::MULADDX_OP2);
3713 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBX_OP1);
3714 setFound(AArch64::MADDXrrr, 2, AArch64::XZR, MCP::MULSUBX_OP2);
3720 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULADDXI_OP1);
3726 setFound(AArch64::MADDXrrr, 1, AArch64::XZR, MCP::MULSUBXI_OP1);
4167 ZeroReg = AArch64::XZR;
4209 ZeroReg = AArch64::XZR;
4259 ZeroReg = AArch64::XZR;
4857 !(DefMI->getOperand(1).getReg() == AArch64::XZR &&
4858 DefMI->getOperand(2).getReg() == AArch64::XZR))
5666 .addReg(AArch64::XZR)
5670 .addReg(AArch64::XZR)
5720 MI.getOperand(1).getReg() == AArch64::XZR &&
lib/Target/AArch64/AArch64InstructionSelector.cpp 1302 I.getOperand(1).ChangeToRegister(AArch64::XZR, false);
1795 I.getOperand(0).setReg(AArch64::XZR);
3179 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
3203 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
3247 ZReg = AArch64::XZR;
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 765 .addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
980 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
lib/Target/AArch64/AArch64MacroFusion.cpp 256 if (FirstMI->definesRegister(AArch64::XZR))
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 209 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
253 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
386 ((IsCopy && (SrcReg == AArch64::XZR || SrcReg == AArch64::WZR)) ||
lib/Target/AArch64/AArch64RegisterInfo.cpp 245 return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
lib/Target/AArch64/AArch64SpeculationHardening.cpp 234 .addUse(AArch64::XZR)
370 .addDef(AArch64::XZR)
377 .addUse(AArch64::XZR)
378 .addUse(AArch64::XZR)
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 2273 .Case("x31", AArch64::XZR)
4575 RegWidth == 32 ? AArch64::WZR : AArch64::XZR, RegKind::Scalar,
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 425 AArch64::LR, AArch64::XZR
456 if (Register == AArch64::XZR)
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 174 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
266 (MI->getOperand(1).getReg() == AArch64::XZR ||
298 (MI->getOperand(0).getReg() == AArch64::XZR ||
739 if (Reg != AArch64::XZR)
901 if (Reg == AArch64::XZR)
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 129 {codeview::RegisterId::ARM64_ZR, AArch64::XZR},
lib/Target/AArch64/Utils/AArch64BaseInfo.h 63 case AArch64::XZR: return AArch64::WZR;
103 case AArch64::WZR: return AArch64::XZR;