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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 5055 extern const TargetRegisterClass GPR32RegClass;
References
gen/lib/Target/AArch64/AArch64GenFastISel.inc 2538 return fastEmitInst_r(AArch64::RBITWr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
2575 return fastEmitInst_r(AArch64::REVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
2597 return fastEmitInst_r(AArch64::CLZWr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3256 return fastEmitInst_r(AArch64::FCVTZSUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3278 return fastEmitInst_r(AArch64::FCVTZSUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3300 return fastEmitInst_r(AArch64::FCVTZSUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3383 return fastEmitInst_r(AArch64::FCVTZUUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3405 return fastEmitInst_r(AArch64::FCVTZUUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3427 return fastEmitInst_r(AArch64::FCVTZUUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3894 return fastEmitInst_r(AArch64::FCVTASUWHr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3915 return fastEmitInst_r(AArch64::FCVTASUWSr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
3931 return fastEmitInst_r(AArch64::FCVTASUWDr, &AArch64::GPR32RegClass, Op0, Op0IsKill);
5957 return fastEmitInst_rr(AArch64::ADDWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
6059 return fastEmitInst_rr(AArch64::ANDWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7021 return fastEmitInst_rr(AArch64::ORRWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7138 return fastEmitInst_rr(AArch64::SDIVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7341 return fastEmitInst_rr(AArch64::SUBSWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7443 return fastEmitInst_rr(AArch64::UDIVWr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7601 return fastEmitInst_rr(AArch64::EORWrr, &AArch64::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
7865 return fastEmitInst_ri(AArch64::UMOVvi32, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1);
7948 return fastEmitInst_ri(AArch64::UMOVvi16, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1);
8014 return fastEmitInst_ri(AArch64::UMOVvi8, &AArch64::GPR32RegClass, Op0, Op0IsKill, imm1);
9133 return fastEmitInst_i(AArch64::MOVi32imm, &AArch64::GPR32RegClass, imm0);
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 6123 &AArch64::GPR32RegClass,
6130 &AArch64::GPR32RegClass,
8199 &AArch64::GPR32RegClass,
lib/Target/AArch64/AArch64CollectLOH.cpp 468 for (MCPhysReg Reg : AArch64::GPR32RegClass)
lib/Target/AArch64/AArch64FastISel.cpp 389 : &AArch64::GPR32RegClass;
421 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
481 ResultReg = createResultReg(&AArch64::GPR32RegClass);
1336 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1379 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1423 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1466 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1763 RC = &AArch64::GPR32RegClass;
1869 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1874 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1879 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
2582 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2601 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2622 unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass);
2703 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2725 RC = &AArch64::GPR32RegClass;
2898 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
3029 RC = &AArch64::GPR32RegClass;
3821 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
3996 ResultReg = createResultReg(&AArch64::GPR32RegClass);
4034 return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
4054 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4093 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4121 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4199 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4228 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4320 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4349 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4472 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4665 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4863 case MVT::i32: RC = &AArch64::GPR32RegClass; break;
4962 RC = &AArch64::GPR32RegClass;
5102 ResRC = &AArch64::GPR32RegClass;
5121 const unsigned ResultReg2 = createResultReg(&AArch64::GPR32RegClass);
5122 const unsigned ScratchReg = createResultReg(&AArch64::GPR32RegClass);
lib/Target/AArch64/AArch64ISelLowering.cpp 3208 RC = &AArch64::GPR32RegClass;
lib/Target/AArch64/AArch64InstrInfo.cpp 629 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) {
630 RC = &AArch64::GPR32RegClass;
1607 return (AArch64::GPR32RegClass.contains(DstReg) ||
2750 AArch64::GPR32RegClass.contains(SrcReg)) {
2755 if (AArch64::GPR32RegClass.contains(DestReg) &&
2831 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
2962 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
3283 if (AArch64::GPR32RegClass.contains(SrcReg)) {
3326 FillRC = &AArch64::GPR32RegClass;
4125 RC = &AArch64::GPR32RegClass;
4140 RC = &AArch64::GPR32RegClass;
4162 RC = &AArch64::GPR32RegClass;
4205 RC = &AArch64::GPR32RegClass;
4232 RC = &AArch64::GPR32RegClass;
4254 RC = &AArch64::GPR32RegClass;
lib/Target/AArch64/AArch64InstructionSelector.cpp 310 : &AArch64::GPR32RegClass;
342 : &AArch64::GPR32RegClass;
1306 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI);
1543 DefSize == 32 ? AArch64::GPR32RegClass : AArch64::GPR64RegClass;
1633 AArch64::GPR32RegClass, MRI);
1668 AArch64::GPR32RegClass, MRI);
1805 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1981 } else if (DstRC == &AArch64::GPR32RegClass &&
2097 if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass, MRI)) {
2241 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
2251 Register Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
3989 AArch64::GPR32RegClass, MRI);
4005 AArch64::GPR32RegClass, MRI);
4559 Register NarrowReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
tools/llvm-exegesis/lib/AArch64/Target.cpp 47 if (AArch64::GPR32RegClass.contains(Reg))