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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12955 { 308 /* blr */, AArch64::BLR, Convert__Reg1_0, AMFBS_None, { MCK_GPR64 }, },
20313 { 308 /* blr */, AArch64::BLR, Convert__Reg1_0, AMFBS_None, { MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenDAGISel.inc96300 /*218016*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::BLR), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
gen/lib/Target/AArch64/AArch64GenFastISel.inc 124 return fastEmitInst_r(AArch64::BLR, &AArch64::GPR64RegClass, Op0, Op0IsKill);
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc11280 case AArch64::BLR:
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc13450 ( MI->getOpcode() == AArch64::BLR )
13458 ( MI->getOpcode() == AArch64::BLR )
13466 ( MI->getOpcode() == AArch64::BLR )
18444 ( MI->getOpcode() == AArch64::BLR )
18452 ( MI->getOpcode() == AArch64::BLR )
18460 ( MI->getOpcode() == AArch64::BLR )
lib/Target/AArch64/AArch64AsmPrinter.cpp 849 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
1058 Blr.setOpcode(AArch64::BLR);
lib/Target/AArch64/AArch64CallLowering.cpp 765 return IsIndirect ? AArch64::BLR : AArch64::BL;
lib/Target/AArch64/AArch64FastISel.cpp 3268 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
3301 const MCInstrDesc &II = TII.get(AArch64::BLR);
lib/Target/AArch64/AArch64FrameLowering.cpp 1081 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BLR))
lib/Target/AArch64/AArch64InstrInfo.cpp 5179 (LastInstrOpcode == AArch64::BLR && !HasBTI)) {
5455 if (MI.getOpcode() == AArch64::BLR || MI.getOpcode() == AArch64::BL)
5542 assert(Call->getOpcode() == AArch64::BLR);
lib/Target/AArch64/AArch64InstructionSelector.cpp 2389 MIB.buildInstr(AArch64::BLR, {}, {Load})