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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12772 { 72 /* adds */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImm }, },
13209 { 661 /* cmn */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR64sp, MCK_AddSubImm }, },
13221 { 665 /* cmp */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
19005 { 5976 /* subs */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImmNeg }, },
20130 { 72 /* adds */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImm }, },
20567 { 661 /* cmn */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR64sp, MCK_AddSubImm }, },
20579 { 665 /* cmp */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
26363 { 5976 /* subs */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImmNeg }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc14889 case AArch64::ADDSXri:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc15605 case AArch64::ADDSXri:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc93482 /*212696*/ OPC_MorphNodeTo2, TARGET_VAL(AArch64::ADDSXri), 0,
93494 /*212724*/ OPC_MorphNodeTo2, TARGET_VAL(AArch64::ADDSXri), 0,
93554 /*212858*/ OPC_MorphNodeTo2, TARGET_VAL(AArch64::ADDSXri), 0,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18069 case AArch64::ADDSXri:
29807 case AArch64::ADDSXri:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 9453 case AArch64::ADDSXri:
lib/Target/AArch64/AArch64CondBrTuning.cpp 229 case AArch64::ADDSXri:
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 172 case AArch64::ADDSXri: {
219 case AArch64::ADDSXri: return AArch64::SUBSXri;
221 case AArch64::SUBSXri: return AArch64::ADDSXri;
247 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
lib/Target/AArch64/AArch64ConditionalCompares.cpp 327 case AArch64::ADDSXri:
663 case AArch64::ADDSXri: Opc = AArch64::CCMNXi; break;
lib/Target/AArch64/AArch64FastISel.cpp 1373 { AArch64::ADDSWri, AArch64::ADDSXri } }
lib/Target/AArch64/AArch64FrameLowering.cpp 192 MI.getOpcode() == AArch64::ADDSXri)
lib/Target/AArch64/AArch64InstrInfo.cpp 441 case AArch64::ADDSXri:
1019 case AArch64::ADDSXri:
1108 case AArch64::ADDSXri:
1109 return MIDefinesZeroReg ? AArch64::ADDSXri : AArch64::ADDXri;
1234 case AArch64::ADDSXri:
1248 return AArch64::ADDSXri;
1377 return Opcode == AArch64::ADDSWri || Opcode == AArch64::ADDSXri;
1885 return AArch64::ADDSXri;
3055 case AArch64::ADDSXri:
3149 unsigned Opc = SetNZCV ? AArch64::ADDSXri : AArch64::ADDXri;
3464 if (Opcode == AArch64::ADDSXri || Opcode == AArch64::ADDXri) {
3468 MachineInstr::NoFlags, (Opcode == AArch64::ADDSXri));
3507 case AArch64::ADDSXri:
3546 case AArch64::ADDSXri:
lib/Target/AArch64/AArch64InstructionSelector.cpp 3174 static const unsigned OpcTable[2][2]{{AArch64::ADDSXrr, AArch64::ADDSXri},
lib/Target/AArch64/AArch64MacroFusion.cpp 35 case AArch64::ADDSXri:
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 177 case AArch64::ADDSXri:
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 4111 case AArch64::ADDSXri: