reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub); 344 (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub); 344 (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub); 366 if (!RR.Sub) 368 BitMask M = mask(RR.Reg, RR.Sub); 382 assert(RR.Sub == 0 && "Unexpected sub-register in definition"); 727 assert(RD.Sub == 0); 747 assert(RD.Sub == 0); 829 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) 836 dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub) 859 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) 877 assert(RD.Sub == 0 && "Unexpected sub-register in definition"); 1001 BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub); 1002 BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub);lib/Target/Hexagon/HexagonBitSimplify.cpp
407 if (RR.Sub == 0) { 419 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) 419 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) 899 if (RR.Sub == 0) 912 VerifySR(RC, RR.Sub); 915 VerifySR(RC, RR.Sub); 1348 .addReg(RS.Reg, 0, RS.Sub); 1349 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 1558 Out.Sub = 0; 1570 Out.Sub = Hexagon::isub_lo; 1572 Out.Sub = Hexagon::isub_hi; 1611 .addReg(MR.Reg, 0, MR.Sub); 1630 .addReg(ML.Reg, 0, ML.Sub) 1632 .addReg(MH.Reg, 0, MH.Sub) 1676 if (RS.Sub != 0) 1677 Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI); 1688 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI); 1689 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); 1699 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, RL.Reg, RL.Sub, MRI); 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); 1709 Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI); 1864 RH.Sub = Sub; 1868 RH.Sub = 0; 1893 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) 1893 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) 1895 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) 1895 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) 1930 ValOp.setSubReg(H.Sub); 2030 .addReg(Rs.Reg, 0, Rs.Sub) 2031 .addReg(Rt.Reg, 0, Rt.Sub); 2032 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2059 .addReg(L.Reg, 0, L.Sub); 2065 .addReg(L.Reg, 0, L.Sub) 2071 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2085 if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low) 2085 if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low) 2101 .addReg(H.Reg, 0, H.Sub) 2102 .addReg(L.Reg, 0, L.Sub); 2103 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2158 .addReg(RS.Reg, 0, RS.Sub); 2163 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2350 RR.Sub = Hexagon::isub_lo; 2353 RR.Sub = Hexagon::isub_hi; 2361 .addReg(RR.Reg, 0, RR.Sub) 2405 assert(RD.Sub == 0); 2459 dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) 2587 assert(RD.Sub == 0); 2662 if (SR.Sub == 0 && InpDef->getOpcode() == Hexagon::C2_muxii) { 3134 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() 3135 << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" 3255 << printReg(G.Inp.Reg, HRI, G.Inp.Sub) 3256 << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";lib/Target/Hexagon/HexagonBitTracker.cpp
1222 assert(RD.Sub == 0);