reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
338 if (Register::isVirtualRegister(RR.Reg)) { 339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub); 342 assert(Register::isPhysicalRegister(RR.Reg)); 344 (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub); 344 (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub); 354 if (Register::isPhysicalRegister(RR.Reg)) 357 assert(Register::isVirtualRegister(RR.Reg)); 360 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg); 364 CellMapType::const_iterator F = M.find(RR.Reg); 368 BitMask M = mask(RR.Reg, RR.Sub); 380 if (!Register::isVirtualRegister(RR.Reg)) 384 M[RR.Reg] = RC.regify(RR.Reg); 384 M[RR.Reg] = RC.regify(RR.Reg); 736 Res.insert(RegisterCell::ref(getCell(RS, Inputs)), mask(RD.Reg, SS)); 737 Res.insert(RegisterCell::ref(getCell(RT, Inputs)), mask(RD.Reg, ST)); 809 if (DefC == RegisterCell::self(DefRR.Reg, DefBW)) // XXX slow 829 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) 831 Changed |= DefC.meet(ResC, DefRR.Reg); 836 dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub) 839 visitUsesOf(DefRR.Reg); 859 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) 878 if (!Register::isVirtualRegister(RD.Reg)) 882 if (!Eval || ResMap.count(RD.Reg) == 0) { 885 RegisterCell RefC = RegisterCell::self(RD.Reg, DefBW); 903 if (V.Type == BitValue::Ref && V.RefI.Reg == RD.Reg) 915 visitUsesOf(RD.Reg); 1000 assert(Map.count(OldRR.Reg) > 0 && "OldRR not present in map"); 1001 BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub); 1002 BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub); 1012 if (V.Type != BitValue::Ref || V.RefI.Reg != OldRR.Reg) 1016 V.RefI.Reg = NewRR.Reg;lib/Target/Hexagon/HexagonBitSimplify.cpp
406 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); 896 if (!Register::isVirtualRegister(RR.Reg)) 898 auto *RC = MRI.getRegClass(RR.Reg); 927 if (!Register::isVirtualRegister(RD.Reg) || 928 !Register::isVirtualRegister(RS.Reg)) 1278 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); 1279 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); 1291 if (!computeUsedBits(RD.Reg, Used)) 1319 if (!BT.has(RD.Reg)) 1321 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); 1329 if (!BT.has(RS.Reg)) 1338 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); 1348 .addReg(RS.Reg, 0, RS.Sub); 1349 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 1537 if (!BT.has(Inp.Reg)) 1539 const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg); 1557 Out.Reg = R; 1575 Out.Reg = R; 1611 .addReg(MR.Reg, 0, MR.Sub); 1630 .addReg(ML.Reg, 0, ML.Sub) 1632 .addReg(MH.Reg, 0, MH.Sub) 1677 Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI); 1677 Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI); 1679 Changed = HBS::replaceReg(RD.Reg, RS.Reg, MRI); 1679 Changed = HBS::replaceReg(RD.Reg, RS.Reg, MRI); 1685 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); 1688 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI); 1688 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI); 1689 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); 1689 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); 1695 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); 1699 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, RL.Reg, RL.Sub, MRI); 1699 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, RL.Reg, RL.Sub, MRI); 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); 1700 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); 1709 Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI); 1709 Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI); 1863 RH.Reg = Reg; 1893 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) 1893 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) 1895 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) 1895 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) 1920 if (!BT.has(RS.Reg)) 1922 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); 1929 ValOp.setReg(H.Reg); 1965 if (!BT.has(RS.Reg)) 1967 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); 2018 if (!matchPackhl(RD.Reg, RC, Rs, Rt)) 2030 .addReg(Rs.Reg, 0, Rs.Sub) 2031 .addReg(Rt.Reg, 0, Rt.Sub); 2032 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2043 if (!matchHalf(RD.Reg, RC, 0, L) || !HBS::isZero(RC, 16, 16)) 2059 .addReg(L.Reg, 0, L.Sub); 2065 .addReg(L.Reg, 0, L.Sub) 2071 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2082 if (!matchHalf(RD.Reg, RC, 0, L) || !matchHalf(RD.Reg, RC, 16, H)) 2082 if (!matchHalf(RD.Reg, RC, 0, L) || !matchHalf(RD.Reg, RC, 16, H)) 2085 if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low) 2085 if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low) 2101 .addReg(H.Reg, 0, H.Sub) 2102 .addReg(L.Reg, 0, L.Sub); 2103 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2143 if (!BT.has(RS.Reg)) 2145 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); 2158 .addReg(RS.Reg, 0, RS.Sub); 2163 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); 2305 HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_lo, MRI); 2309 HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_hi, MRI); 2333 if (!BT.has(RS.Reg) || !HBS::getSubregMask(RS, F, W, MRI)) 2339 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); 2341 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg != RS.Reg) { 2361 .addReg(RR.Reg, 0, RR.Sub) 2363 HBS::replaceReg(RD.Reg, NewR, MRI); 2371 HBS::replaceReg(RD.Reg, NewR, MRI); 2425 if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg == RD.Reg) 2444 if (TopV.RefI.Reg == RD.Reg || TopV.RefI.Pos == W-1) 2459 dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) 2566 HBS::replaceReg(RD.Reg, NewR, MRI); 2597 if (!BT.has(SR.Reg)) 2599 const BitTracker::RegisterCell &SC = BT.lookup(SR.Reg); 2616 HBS::replaceReg(RD.Reg, NewR, MRI); 2659 MachineInstr *InpDef = MRI.getVRegDef(SR.Reg); 2683 HBS::replaceReg(RD.Reg, NewR, MRI); 2726 if (!BT.has(RD.Reg)) 2729 const BitTracker::RegisterCell &RC = BT.lookup(RD.Reg); 3075 .addReg(G.Inp.Reg) 3077 RegMap.insert(std::make_pair(G.Inp.Reg, PhiR)); 3101 HBS::replaceReg(OldPhiR, RegMap[G.Out.Reg], *MRI); 3134 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() 3135 << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" 3216 G.Out.Reg = getDefReg(SI); 3242 return G.Out.Reg == P.LR.Reg; 3242 return G.Out.Reg == P.LR.Reg; 3247 G.Inp.Reg = Inputs.find_first(); 3255 << printReg(G.Inp.Reg, HRI, G.Inp.Sub) 3256 << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; 3264 if (!isShuffleOf(G.Out.Reg, G.Inp.Reg)) 3264 if (!isShuffleOf(G.Out.Reg, G.Inp.Reg)) 3267 return G.Out.Reg == P.LR.Reg; 3267 return G.Out.Reg == P.LR.Reg; 3273 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PrehR)) { 3273 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PrehR)) { 3273 if (!isSameShuffle(G.Out.Reg, G.Inp.Reg, F->PR.Reg, PrehR)) { 3274 const MachineInstr *DefPrehR = MRI->getVRegDef(F->PR.Reg); 3282 const TargetRegisterClass *RC = MRI->getRegClass(G.Inp.Reg); 3283 if (RC != MRI->getRegClass(F->PR.Reg)) { 3292 PrehR = F->PR.Reg; 3300 if (MRI->getRegClass(PrehR) != MRI->getRegClass(G.Inp.Reg))lib/Target/Hexagon/HexagonBitTracker.cpp
313 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; 316 unsigned Reg0 = Reg[0].Reg; 335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); 358 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); 440 RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0); 815 R2.meet(R3, Reg[0].Reg); 1198 Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i)); 1223 if (!Register::isPhysicalRegister(RS.Reg)) 1225 RegExtMap::const_iterator F = VRX.find(RD.Reg);