reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
746 Register Reg0 = MI->getOperand(0).getReg(); 747 Register Reg1 = MI->getOperand(1).getReg(); 749 if (MI->getOpcode() == ARM::t2MUL) { 750 Register Reg2 = MI->getOperand(2).getReg(); 761 MachineInstr *CommutedMI = TII->commuteInstruction(*MI); 769 if (!TII->findCommutedOpIndices(*MI, CommOpIdx1, CommOpIdx2) || 770 MI->getOperand(CommOpIdx2).getReg() != Reg0) 773 TII->commuteInstruction(*MI, false, CommOpIdx1, CommOpIdx2); 780 unsigned Imm = MI->getOperand(2).getImm(); 785 Register Reg2 = MI->getOperand(2).getReg(); 793 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); 805 const MCInstrDesc &MCID = MI->getDesc(); 808 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); 809 if (HasCC && MI->getOperand(NumOps-1).isDead()) 812 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead)) 818 canAddPseudoFlagDep(MI, IsSelfLoop)) 822 DebugLoc dl = MI->getDebugLoc(); 823 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); 824 MIB.add(MI->getOperand(0)); 830 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 835 MIB.add(MI->getOperand(i)); 839 MIB.setMIFlags(MI->getFlags()); 841 LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI 844 MBB.erase_instr(MI);